Estimation of Remaining Useful Life (RUL) is a crucial task in Prognostics and Health Management (PHM) for condition-based maintenance of machinery. In order to transmit and store the sensor data for archiving and long term analysis, data compression techniques are regularly used to reduce the requirements of bandwidth, energy and storage in modern remote PHM systems. In these systems the challenge arises of how the compressed sensor data affects the RUL estimation algorithms. A main drawback of conventional statistical modeling approaches is that they require expert prior knowledge and a significant number of assumptions. Alternative regression based approaches and deep neural networks are known to have issues when modeling long-term dependencies in the sequential data. Recently Long Short-Term Memory (LSTM) neural networks have been proposed to overcome these issues and in this paper we create a LSTM network and data fusion approach that can estimate the RUL with compressed (distorted) data. The experimental results indicate that the proposed method is able to estimate RUL reliably with narrower error bands compared to other state-of-the-art approaches. Moreover, the proposed method is able to predict RUL from both the raw and compressed datasets with comparable accuracy. INDEX TERMS Machine health monitoring, remaining useful life (RUL), long-short term memory, recurrent neural network, data compression.
Power is an important issue limiting the applicability of Field Programmable Gate Arrays (FPGAs) since it is considered to be up to one order of magnitude higher than in ASICs. Recently, dynamic reconfiguration in FPGAs has emerged as a viable technique able to achieve power and cost reductions by time-multiplexing the required functionality at runtime. In this article, the applicability of Adaptive Voltage Scaling (AVS) to FPGAs is considered together with dynamic reconfiguration of logic and clock management resources to further improve the power profile of these devices. AVS is a popular power-saving technique in ASICs that enables a device to regulate its own voltage and frequency based on workload, fabrication, and operating conditions. The resulting processing platform exploits the available application-dependent timing margins to achieve a power reduction up to 85% operating at 0.58 volts compared with operating at a nominal voltage of 1 volt. The results also show that the energy requirements at 0.58 volts are aproximately five times lower compared with nominal voltage and this can be explained by the approximate cubic relation of static energy with voltage and the fact that the static component dominates power consumption in the considered FPGA devices.
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