Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform

Nabina, A.; Nunez-Yanez, Jose

doi:10.1145/2392616.2392618

Cited by 24 publications

(22 citation statements)

References 14 publications

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“…For performing all the processing at run-time, several works have been reported [8], [15], [16], [22]- [24]. In [22], the online algorithm utilizes hardware performance monitoring counters (PMCs) to achieve energy savings without recompiling the applications.…”

Section: Related Workmentioning

confidence: 99%

“…A similar approach, which is a hardware-specific implementation of the stall-based model, is proposed in [15]. In [24], an adaptive DVFS approach for FPGA-based video motion compensation engines using run-time measurements of the underlying hardware is introduced. In [8], online reinforcement learning based adaptive DVFS is performed to achieve energy savings.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Inter-Cluster Thread-to-Core Mapping and DVFS on Heterogeneous Multi-Cores

Basireddy

Singh

Biswas

et al. 2018

IEEE Trans. Multi-Scale Comp. Syst.

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Abstract-Heterogeneous multi-core platforms that contain different types of cores, organized as clusters, are emerging, e.g. ARM's big.LITTLE architecture. These platforms often need to deal with multiple applications, having different performance requirements, executing concurrently. This leads to generation of varying and mixed workloads (e.g. compute and memory intensive) due to resource sharing. Run-time management is required for adapting to such performance requirements and workload variabilities and to achieve energy efficiency. Moreover, the management becomes challenging when the applications are multi-threaded and the heterogeneity needs to be exploited. The existing run-time management approaches do not efficiently exploit cores situated in different clusters simultaneously (referred to as inter-cluster exploitation) and DVFS potential of cores, which is the aim of this paper. Such exploitation might help to satisfy the performance requirement while achieving energy savings at the same time. Therefore, in this paper, we propose a run-time management approach that first selects thread-to-core mapping based on the performance requirements and resource availability. Then, it applies online adaptation by adjusting the voltage-frequency (V-f) levels to achieve energy optimization, without trading-off application performance. For thread-to-core mapping, offline profiled results are used, which contain performance and energy characteristics of applications when executed on the heterogeneous platform by using different types of cores in various possible combinations. For an application, thread-to-core mapping process defines the number of used cores and their type, which are situated in different clusters. The online adaptation process classifies the inherent workload characteristics of concurrently executing applications, incurring a lower overhead than existing learning-based approaches as demonstrated in this paper. The classification of workload is performed using the metric Memory Reads Per Instruction (MRPI). The adaptation process pro-actively selects an appropriate V-f pair for a predicted workload. Subsequently, it monitors the workload prediction error and performance loss, quantified by instructions per second (IPS), and adjusts the chosen V-f to compensate. We validate the proposed run-time management approach on a hardware platform, the Odroid-XU3, with various combinations of multi-threaded applications from PARSEC and SPLASH benchmarks. Results show an average improvement in energy efficiency up to 33% compared to existing approaches while meeting the performance requirements.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Inter-Cluster Thread-to-Core Mapping and DVFS on Heterogeneous Multi-Cores

Basireddy

Singh

Biswas

et al. 2018

IEEE Trans. Multi-Scale Comp. Syst.

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“…allocating a task to a computing resource) [7]. Moreover, to adapt to dynamic workload and application performance variations, such control will need to be coupled with DVFS [8].…”

Section: Introductionmentioning

confidence: 99%

“…Conversely, when the CPU usage increases, the operating frequency is increased to the maximum point. Nabina and NunezYanez [8] showed a DVFS approach for FPGA-based video motion compensation engines. Their approach uses applicationspecific requirements to monitor the available timing margins per motion compensation task and control the operating voltage/ frequency accordingly.…”

Section: Introductionmentioning

confidence: 99%

Adaptive energy minimization of embedded heterogeneous systems using regression-based learning

Yang

Shafik

Merrett

et al. 2015

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Abstract-Modern embedded systems consist of heterogeneous computing resources with diverse energy and performance trade-offs. This is because the computing resources exercise the application tasks differently, generating varying workloads and energy consumption. As a result, minimizing energy consumption in these systems is challenging as it requires continuous adaptation of application task mapping (i.e. allocating tasks among the computing resources) and dynamic voltage/frequency scaling (DVFS). Existing approaches lack such adaptation with practical validation (Table I). This paper proposes a novel adaptive energy minimization approach for embedded heterogeneous systems. Fundamental to this approach is a runtime model, generated through regression-based learning of energy/performance trade-offs between different computing resources in the system. Using this model, an application task is suitably mapped on a computing resource during runtime, ensuring minimum energy consumption for a given application performance requirement. Such mapping is also coupled with a DVFS control to adapt to performance and workload variations. The proposed approach is designed, engineered and validated on a Zynq-ZC702 platform, consisting of CPU, DSP and FPGA cores. Using several image processing applications as case studies, our proposed approach can achieve significant energy savings (70% in some cases, i.e. from 43mJ per frame to 13 mJ per frame), when compared to existing approaches.

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“…Modern FPGAs provide support for partial dynamic reconfiguration [26], i.e., parts of the device may be reconfigured at run time, while the other parts remain fully functional. Considering these advantages, FPGAs have been applied in a variety of applications: e.g., performance enhancement [3,11] and, more recently, low-power and energy-efficient applications [22,21,15]. In this paper, we will utilize the available FPGA in the design of energy-efficient secure embedded systems.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Energy-aware design of secure multi-mode real-time embedded systems with FPGA co-processors

Jiang

Lifa

Eles

et al. 2013

Proceedings of the 21st International Conference on Real-Time Networks and Systems

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We approach the emerging area of energy efficient, secure real-time embedded systems design. Many modern embedded systems have to fulfill strict security constraints and are often required to meet stringent deadlines in different operation modes, where the number and nature of active tasks vary (dynamic task sets). In this context, the use of dynamic voltage/frequency scaling (DVFS) techniques and onboard field-programmable gate array (FPGA) co-processors offer new dimensions for energy savings and performance enhancement. We propose a novel design framework that provides the best security protection consuming the minimal energy for all operation modes of a system. Extensive experiments demonstrate the efficiency of our techniques.

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Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform

Cited by 24 publications

References 14 publications

Inter-Cluster Thread-to-Core Mapping and DVFS on Heterogeneous Multi-Cores

Inter-Cluster Thread-to-Core Mapping and DVFS on Heterogeneous Multi-Cores

Adaptive energy minimization of embedded heterogeneous systems using regression-based learning

Energy-aware design of secure multi-mode real-time embedded systems with FPGA co-processors

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