Abstract— In this paper, the effect of source/drain overlap length on the amorphous indium gallium zinc oxide (a‐IGZO) TFT performance has been investigated. Results of this paper show that as source/drain overlap length decreases to a negative value forming S/D offset, the threshold voltage and S parameters of a‐IGZO TFTs increased and the field‐effect mobility decreased. The VT variation increases sharply as the channel length decreases because of the large resistance Roffset when it is formed at a‐IGZO source/drain. In the experiment, Roffset of each 1 μm, evaluated from the transfer length method (TLM), shows approximately 54–66 kΩ. This means thatthe source/drain overlap length is a very important control parameter for uniform device characteristics of a‐IGZO TFTs.
We synthesized lamellar-structured silica thin films with various repeating distances in the range 5.9-8.8 nm. The synthesis was achieved through the self-assembly of a silica precursor (tetraethoxyorthosilicate) and a non-ionic triblock copolymer F-127 ((EO) 106 (PO) 70 (EO) 106 , EO ¼ ethylene oxide, PO ¼ propylene oxide), followed by calcination. The lamellar structure was unambiguously confirmed by small angle X-ray diffraction, grazing incidence small angle X-ray scattering, transmission electron microscopy, and atomic force microscopy. The lamellar structure can be understood as being composed of alternating high density and low density silica layers. The successful synthesis requires the right compositions of the coating solutions and a high spin-speed ($6000 rpm) during the spin-coating of the solutions. Mechanisms for the formation of the lamellar structure and its maintenance after the surfactant removal were proposed. Such a structure exhibits remarkable properties, including very high thermal stability up to 800 C and unusually high mechanical properties for nanostructured silica films.
We have fabricated the flexible pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics treated by CF4/O2 plasma on poly[ethersulfones] (PES) substrate. The solution of gate dielectrics is made by adding methylated poly[melamine-co-formaldehyde] (MMF) to PVP. The PVP gate dielectric layer was cross linked at 90 degrees under UV ozone exposure. Source/drain electrodes are formed by micro contact printing (MCP) method using nano particle silver ink for the purposes of low cost and high throughput. The optimized OTFT shows the device performance with field effect mobility of the 0.88 cm2/V s, subthreshold slope of 2.2 V/decade, and on/off current ratios of 1.8 x 10(-6) at -40 V gate bias. We found that hydrophobic PVP gate dielectric surface can influence on the initial film morphologies of pentacene making dense, which is more important for high performance OTFTs than large grain size. Moreover, hydrophobic gate dielelctric surface reduces voids and -OH groups that interrupt the carrier transport in OTFTs.
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