We present the results of a combined multichannel seismic reflection (MCS) and wide-angle, ocean bottom seismic profile collected in 1988 across the Carolina Trough on the U.S. Atlantic continental margin. Inversion of vertical-incidence and wide-angle travel time data has produced a velocity model of the entire crust across the continent-ocean transition. The margin consists of three structural elements: (1) rifted continental crust, comprising 1-4 km of post-rift sedimentary rocks overlying a 30-34 km thick subsedimentary crust, (2) transitional crust, a 70-to 80-kin-wide zone comprising up to 12 km of postrift sedimentary rocks overlying a 10-to 24-km-thick subsedimentary crust, and (3) oceanic crust, comprising 8 km of sedimentary rocks overlying an 8-km-thick crystalline crust. The boundary between rifted continental and transitional crust, marked by the Brunswick magnetic anomaly, represents an abrupt change in physical properties, with strong lateral increases in seismic velocity, density, and magnetic susceptibility. The transitional crust contains mid-crustal seaward-dipping reflections observed on the MCS section and has seismic velocities of 6.5-6.9 km/s in the midcrust and 7.2-7.5 km/s in the lower crust. Modeling of potential field data shows that transitional crust also produces the prominent, margin-parallel gravity anomaly and the Brunswick and East Coast magnetic anomalies. These observations support the interpretation that the transitional crust was formed by magmatism during continental breakup. The prodigious thickness (up to 24 km) of igneous material rivals that interpreted on continental margins of the North Atlantic (e.g., Hatton Bank and V0ring Plateau), which formed in the vicinity of the Iceland hotspot. These observations, when combined with other transects across the margin, confirm previous suggestions that the U.S. Atlantic margin is strongly volcanic and further imply that the magmatism was not the result of a long-lived mantle plume. Introduction Passive, or rifted, margins are formed by the breakup of a continent and birth of a new ocean basin. The crustal architecture of a passive margin thus holds important records of the processes attending continental rifting and early seafloor spreading, such as faulting [e.g., Klitgord and Behrendt, 1979], thermal and tectonic subsidence [e.g., Sawyer, 1985; Steckler and Watts, 1978], ductile thinning, and volcanism [e.g., Mutter et al., 1984; White et al., 1987]. Crucial to understanding these processes is the zone between the basement hinge and the landward limit of oceanic crust 1Department of Geology and Geophysics, Woods Hole Oceanographic Institution, Woods Hole, Massachusetts. (usually called transitional or rift-stage crust [Klitgord et al., 1988]); yet this region is least well-constrained by existing data. Imaging the deep structure of continental margins has long been an elusive goal. Multichannel seismic (MCS) data have provided many new insights, including the observation on several margins of seaward-dipping reflections interp...
Nanoelectromechanical (NEM) switches have received widespread attention as promising candidates in the drive to surmount the physical limitations currently faced by complementary metal oxide semiconductor technology. The NEM switch has demonstrated superior characteristics including quasi-zero leakage behaviour, excellent density capability and operation in harsh environments. However, an unacceptably high operating voltage (4-20 V) has posed a major obstacle in the practical use of the NEM switch in low-power integrated circuits. To utilize the NEM switch widely as a core device component in ultralow power applications, the operation voltage needs to be reduced to 1 V or below. However, sub-1 V actuation has not yet been demonstrated because of fabrication difficulties and irreversible switching failure caused by surface adhesion. Here, we report the sub-1 V operation of a NEM switch through the introduction of a novel pipe clip device structure and an effective air gap fabrication technique. This achievement is primarily attributed to the incorporation of a 4-nm-thick air gap, which is the smallest reported so far for a NEM switch generated using a 'top-down' approach. Our structure and process can potentially be utilized in various nanogap-related applications, including NEM switch-based ultralow-power integrated circuits, NEM resonators, nanogap electrodes for scientific research and sensors.
ObjectiveTo evaluate the interobserver variability and performance in the interpretation of ultrasonographic (US) findings of thyroid nodules.Materials and Methods72 malignant nodules and 61 benign nodules were enrolled as part of this study. Five faculty radiologists and four residents independently performed a retrospective analysis of the US images. The observers received one training session after the first interpretation and then performed a secondary interpretation. Agreement was analyzed by Cohen's kappa statistic. Degree of performance was analyzed using receiver operating characteristic (ROC) curves.ResultsAgreement between the faculties was fair-to-good for all criteria; however, between residents, agreement was poor-to-fair. The area under the ROC curves was 0.72, 0.62, and 0.60 for the faculties, senior residents, and junior residents, respectively. There was a significant difference in performance between the faculties and the residents (p < 0.05). There was a significant increase in the agreement for some criteria in the faculties and the senior residents after the training session, but no significant increase in the junior residents.ConclusionIndependent reporting of thyroid US performed by residents is undesirable. A continuous and specialized resident training is essential to enhance the degree of agreement and performance.
Sub-5nm all-around gate FinFETs with 3nm fin width were fabricated for the first time. The n-channel FinFET of sub-5nm with 1.4nm HfO 2 shows an I Dsat of 497µA/µm at V G =V D =1.0V. Characteristics of sub-5nm transistor are verified by using 3-D simulations as well as analytical models. A threshold voltage increases as the fin width reduces by quantum confinement effects. The threshold voltage shift was fitted to a theoretical model with consideration of the first-order perturbation theory. And a channel orientation effect, based on a current-flow direction, is shown. Key words: all-around gate, FinFET, sub-5nm, quantum effect Introduction Silicon-based transistors are scaled down continually in order to increase a density and speed. Multi-gate FinFETs have strengths of high robustness on short-channel effects (SCEs) and superior scalability using conventional processes [1][2][3][4][5][6][7]. However, the ultimate minimum feature-sized device operating at room temperature has been expected to be 1.5nm according to Heisenberg's uncertainty principle and Shannon-von NeumannLandauer expression [8]. The fabricated sub-5nm all-around gate (AAG) FinFET is approaching to this fundamental limit. FinFET [7]. For ultimately scaled transistor, AAG FinFET is known to be the best structure to provide scalability and flexibility in device design [9]. This work primarily focuses on feasibility and scalability of sub-5nm AAG FinFET. A threshold voltage shift by quantum confinement and an effect of current-flow direction are reported.Fabrications Fig. 1 illustrates a process flow of AAG FinFET. As a starting material, (100) SOI wafers were used. 100nm silicon film was thinned down to 14nm by using thermal oxidations and HF wet etch. Dual-resist process for a fin and a gate patterning was used to define nanometer features by e-beam lithography and non-critical large-area patterns by optical lithography. After the silicon-fin etch, a sacrificial oxide was grown and removed to alleviate etching damages. Gate dielectrics were split into 1.4nm HfO 2 by atomic layer deposition and 2nm thermal SiO 2 . Reasonable characteristics of sub-5nm devices were achieved in HfO 2 group. 30nm in-situ n + poly-silicon was deposited for the gate electrode. The gate was patterned by the dual-resist process, similarly. After the gate and spacer formation, arsenic ions were implanted to form the source and drain (S/D). 1000℃ spike annealing was utilized to activate the dopants of S/D. Finally, forming gas annealing at 450℃ was applied. Metallization was skipped for iterative annealing to optimize gate-to-S/D overlap. The fabricated device dimensions are sub-5nm gate length (L G ), averaged 3nm fin width (W Fin ), and 14nm fin height (H Fin ).Results and Discussions Fig. 2 shows a SEM top-view of 3nm silicon-fin and sub-5nm gate. Fig. 3 and Fig. 4 show TEM cross-sectional views of 3nm silicon-fin (a-a' direction of Fig. 6 and Fig. 7. An on-state current is 497µA/µm at V G =V D =1.0V in Fig. 6, which is normalized by allarounded channel perime...
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