High-end microprocessors now tend to be superscalar, to execute operations out of order, and to support shared memory among multiple processors. Verifying the functionality of such a microprocessor using simulation requires many stages, from tests of simple portions of the design, through simple tests of a single processor to complex tests of multiple pracessors. We followed this strategy using some already existing tools and writing some new tests and tools. We describe in this paper the general strategy and the tool set we created to perform the final simulation stage of design verification: running complex tests on a model of a multiprocessor system. This tool set operates on the principle that tests which mimic real programs are more likely to uncover errors that customers would encounter. Our results show that random realistic tests can get better coverage of common multiprocessor scenarios in fewer cycles than purely random tests.
Multiprocessing (MP) design verification has been one of the bottlenecks for high performance microprocessor design projects. The problem is getting worse as the design complexity increases and more cache structures are integrated into one single chip. The challenges that MP verification faces today include: huge chip/system simulation model sizes, long simulation cycles, relative inefficiency of the simulation tools compared to uniprocessor, and so on. To solve these challenging problems, we developed a new methodology and simulation flow for an upcoming design in Motorola's G4 generation of microprocessors, MPC74XX 1 . The key strategy of this methodology was to start MP verification as early as the design implementation started. The same methodology/tool set were first developed for MP verification at the unit level, then reused at the multiple-unit level, and eventually reused at the chip/ system level. In this paper, we will present the details of this methodology, and demonstrate why it is effective and efficient in detecting the majority of the MP functional defects at an early stage of the design phase.
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