Multiprocessing design verification methodology for Motorola MPC74XX PowerPC microprocessor

Abstract

Multiprocessing (MP) design verification has been one of the bottlenecks for high performance microprocessor design projects. The problem is getting worse as the design complexity increases and more cache structures are integrated into one single chip. The challenges that MP verification faces today include: huge chip/system simulation model sizes, long simulation cycles, relative inefficiency of the simulation tools compared to uniprocessor, and so on. To solve these challenging problems, we developed a new methodology and simulation flow for an upcoming design in Motorola's G4 generation of microprocessors, MPC74XX 1 . The key strategy of this methodology was to start MP verification as early as the design implementation started. The same methodology/tool set were first developed for MP verification at the unit level, then reused at the multiple-unit level, and eventually reused at the chip/ system level. In this paper, we will present the details of this methodology, and demonstrate why it is effective and efficient in detecting the majority of the MP functional defects at an early stage of the design phase.

A generic micro-architectural test plan approach for microprocessor verification

“…It is especially important to search for bugs at the microarchitectural level, hence the greater effort in this field [2][4] [5][6] [7]. The importance of verification at this level can be seen from the fact that design bugs and their fixes are commonly explained at the micro-architectural level.…”

Stimuli generation with late binding of values

“…In current industrial practice, most of the verification is done using generating a massive amount of tests by random test generators [2,6,11]. The use of advanced random test generators can increase the quality of generated tests, but it cannot ensure that all the "dark corners" in the design are exposed and that the entire test plan is implemented.…”