A generic micro-architectural test plan approach for microprocessor verification

Abstract

Modern microprocessors share several common types of microarchitectural building blocks. The rising complexity of the microarchitecture increases the risk of bugs and the difficulty of achieving comprehensive verification. We propose a methodology to exploit the commonality in the different microprocessors to create a designindependent micro-architectural test plan. Our method allows the testing of the huge micro-architectural test space by using systematic partitioning, which offers a high level of comprehensiveness of the tested behaviors. We show how this method was used to find bugs during verification of an actual high-end microprocessor. Our results show the advantages of this approach over the more traditional test methods that use design specific test plans or that use tools with little micro-architectural knowledge for covering micro-architectural aspects of the design.

Automatic Microprocessor Performance Bug Detection

“…These simplifications make the methodology unable to localize bugs that are not necessarily related to state transitions or dependencies. Adir et al [4] perform a microarchitectural-level verification based on a test plan created by coverage models. These coverage models however, require "creativity" and significant domain knowledge.…”

“…Works in automating microprocessor performance bug localization are even scarcer. Adir et al [4] propose perhaps the only partially related work of which we are aware. Their work focuses on formal planning of test program generation for individual units, such as issue queues.…”

“…These data-driven techniques achieve high accuracy, while being fully automated. Further, they consider intra-and interunit interactions, as opposed to other techniques proposed in the partially related previous work [4] which considered only intra-unit behavior.…”