A generic micro-architectural test plan approach for microprocessor verification

Adir, A.; Azatchi, Hezi; Bin, E.; Peled, O.; Shoikhet, K.

doi:10.1109/dac.2005.193919

Cited by 3 publications

(3 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The ideas discussed in [29]- [32] use constraint solvers to generate tests for functional verification of higher-level architectural features. One of the recent results reported in literature dealing with micro-architecture verification [33] concentrates on using a generic-test-plan (GTP) approach to generate tests. However, the paper does not explain how to generate directed tests that verify specific micro-architectural features.…”

Section: Previous Workmentioning

confidence: 99%

“…However, the paper does not explain how to generate directed tests that verify specific micro-architectural features. A comprehensive survey of many test generation techniques for processor verification is presented in [33]. Employing genetic algorithms to evolve efficient test benches for behavioral level circuit models is studied in [34] and [35].…”

Section: Previous Workmentioning

confidence: 99%

See 1 more Smart Citation

Automatic Constraint Based Test Generation for Behavioral HDL Models

Hari

Konda

Kamakoti

et al. 2008

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

With the emergence of complex high-performance microprocessors, functional test generation has become a crucial design step. Constraint-based test generation is a well-studied directed behavioral level functional test generation paradigm. The paradigm involves conversion of a given circuit model into a set of constraints and employing constraint solvers to generate tests for it. However, automatic extraction of constraints from a given behavioral hardware design language (HDL) model remained a challenging open problem. This paper proposes an approach for automatic extraction of word-level model constraints from the behavioral verilog HDL description. The scenarios to be tested are also expressed as constraints. The model and the scenario constraints are solved together using an integer solver to arrive at the necessary functional test. The effectiveness of the approach is demonstrated by automatically generating the constraint models for: 1) an exclusive-shared-invalid multiprocessor cache coherency model and 2) the 16-bit DLX-architecture, from their respective Verilog-based behavioral models. Experimental results that generate test vectors for high level scenarios like pipeline hazards, cache miss, etc., spanning over multiple time-frames are presented.

show abstract

Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

Automatic Constraint Based Test Generation for Behavioral HDL Models

Hari

Konda

Kamakoti

et al. 2008

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…Also, formal verification is good at verifying individual unit in a design. But many bugs exist in the interface between the units, it is important to test the micro-architecture at the chip level [6] [13]. Therefore, in this paper, we use the simulation-based verification approach.…”

Section: Related Workmentioning

confidence: 99%

Automatic verification of external interrupt behaviors for microprocessor design

Yang

Huang

2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

View full text Add to dashboard Cite

Interrupt behaviors, especially the external ones, are difficult to verify in a microprocessor design project in that they involve both interacting hardware and software. This paper proposes a CAD tool, called PEVT, to verify the external interrupt behaviors of microprocessors. An architecture description language extension, called EXPDL, is developed for the designer to capture the external interrupt behaviors for the microprocessor. PEVT is responsible to generate the verification cases, consisting of both the hardware and software modules, which are then used to trigger the expected behaviors. A monitor is also generated from the EXPDL description to verify these cases. PEVT has been applied to the verification of an academic implementation of ARM7 microprocessor core, which has had a SoC test chip and software porting including MP3 decoder and uC-OSII. PEVT successfully identified several sophisticated remaining bugs with only less than 88,000 cycles of RTL simulation with execution time of 424 seconds in a SUN Blade2000 workstation. The experiment shows that PEVT could generate highly focused verification cases, less than 21 cycles per case on the average, which identify potential bugs with much less simulation cycles, compared with traditional regression tests which consume huge amount of simulation cycles.

show abstract