Automatic Constraint Based Test Generation for Behavioral HDL Models

Abstract

With the emergence of complex high-performance microprocessors, functional test generation has become a crucial design step. Constraint-based test generation is a well-studied directed behavioral level functional test generation paradigm. The paradigm involves conversion of a given circuit model into a set of constraints and employing constraint solvers to generate tests for it. However, automatic extraction of constraints from a given behavioral hardware design language (HDL) model remained a challenging open problem. This paper proposes an approach for automatic extraction of word-level model constraints from the behavioral verilog HDL description. The scenarios to be tested are also expressed as constraints. The model and the scenario constraints are solved together using an integer solver to arrive at the necessary functional test. The effectiveness of the approach is demonstrated by automatically generating the constraint models for: 1) an exclusive-shared-invalid multiprocessor cache coherency model and 2) the 16-bit DLX-architecture, from their respective Verilog-based behavioral models. Experimental results that generate test vectors for high level scenarios like pipeline hazards, cache miss, etc., spanning over multiple time-frames are presented.

Constraint-Based Testing

“…Despite theoretical limitations of automatic test case generation 2 , dealing with these hard combinatorial problems for real-world programs is challenging. Constraint-based testing was introduced to tackle these problems for various applications, including automatic white-box test inputs generation for imperative programs [3][4][5][6][7][8][9][10][11][12] and object-oriented programs [13][14][15][16][17][18], test pattern generation in hardware design [19][20][21], model-based test cases generation [22][23][24][25][26][27], and counter-examples generation [28][29][30][31].…”

Beyond test pattern generation: Coverage analysis

“…However the ATPGs employed at the gate level incur higher cost and design complexity. Many hierarchical test generations at the RTL have been proposed in [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16] and overcome the issues at the gate level test generation.…”

Functional broadside tests for embedded logic blocks

“…1, it is possible to first extract the constraints imposed by B 1 on the input sequences of B 2 [14,15]. It is then possible to use the constraints during functional broadside test generation for B 2 .…”

“…The advantage of this approach is that it allows B 1 and B 2 to be considered separately. However, the procedures described in [14,15] represent the constraints at higher levels than the gate level used for functional broadside test generation [7]. In addition, the constraints may be complex, and it may be difficult to incorporate them into the functional test generation process.…”