Multiprocessor design verification with generated realistic MP programs

Abstract

High-end microprocessors now tend to be superscalar, to execute operations out of order, and to support shared memory among multiple processors. Verifying the functionality of such a microprocessor using simulation requires many stages, from tests of simple portions of the design, through simple tests of a single processor to complex tests of multiple pracessors. We followed this strategy using some already existing tools and writing some new tests and tools. We describe in this paper the general strategy and the tool set we created to perform the final simulation stage of design verification: running complex tests on a model of a multiprocessor system. This tool set operates on the principle that tests which mimic real programs are more likely to uncover errors that customers would encounter. Our results show that random realistic tests can get better coverage of common multiprocessor scenarios in fewer cycles than purely random tests.

VLIW - a case study of parallelism verification

“…In response, we described a parallel test generation technique and reported on experiments that demonstrate its superiority along several dimensions of test quality. Our results are applicable to the verification of other types of parallelism in processor architectures, such as Superscalar, Multithreaded, and Multi-processor designs [4]. In particular, our conclusion that manual enhancements to sequential test generation are bound to fail, is general enough.…”

Targeted random test generation for power-aware multicore designs

“…Realistic but short MP tests are automatically generated in Sullivan et al [1995]. Adir et al [2002] develop colliding concurrent tests by strategic address assignments.…”