VLIW - a case study of parallelism verification

Abstract

Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper we report on the verification of a Very Large Instruction Word processor. The verification team used a sophisticated test program generator that modeled the parallel aspects as sequential constraints, and augmented the tool with manually written test templates. The system created large numbers of legal stimuli, however the quality of the tests was proved insufficient by several post silicon bugs. We analyze this experience and suggest an alternative, parallel generation technique. We show through experiments the feasibility of the new technique and its superior quality along several dimensions. We claim that the results apply to other parallel architectures and verification environments.

DVGen: Increasing Coverage by Automatically Combining Test Specifications

“…However, the reliance on some high level knobs to cover the complex corner cases contrasts with DVGen's directedrandom approach of relying on mixing of different tests in interesting ways to create more complex corner cases. The tool was further augmented with a constraint specification language and a constraint solver and applied [12] on a simple VLIW example design to automatically generate fully packed 1-4244-0679-X/06/$20.00 ©2006 IEEE VLIW instructions. While this is promising, it is not directly applicable for our purpose since the number of constraints to capture the conditions to formulate a legal molecule in our design would be huge and, based on our experience, likely exceed the capacity of modern constraint solver engines.…”