DVGen: Increasing Coverage by Automatically Combining Test Specifications

Abstract

DVGen is a novel microprocessor test generator that allows the verification engineer to focus only on capturing test intent via minimally constrained test specifications. DVGen combines test specifications to generate tests that preserve the intent of each specification while causing the concurrent occurrence of interesting events from each specification. DVGen is very effective at uncovering multi-dimensional corner case bugs, which have historically been the bane of complex designs.