A 780 MHz PowerPC/sup TM/ microprocessor with integrated L2 cache

Bearden, David; Caffo, David G.; Anderson, Paul M.; Rossbach, P.; Iyengar, N.; Petersen, T.A.; Yen, Jen-Tien

doi:10.1109/isscc.2000.839704

Cited by 16 publications

(8 citation statements)

References 2 publications

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“…Stand-alone SRAM, which today has important uses both for cache and in signal processing systems, will probably become part of a larger on-chip system in the future. For instance, a recent microprocessor unit (MPU) [88] features 32-kB instruction and data caches as well as an on-chip 256-kB L2 cache. In the future the L1 cache is likely to increase fairly slowly in size to maintain its high speed, whereas several megabytes of L2 cache might eventually be used and perhaps even additional levels of hierarchy would be incorporated on chip.…”

Section: Sram Limitsmentioning

confidence: 99%

“…Burnett et al [78] investigated cell stability under random dopant fluctuations and showed how this leads to increased voltage requirements for the cell in scaled technologies. In practice, redundancy techniques can and are being used to reduce the impact of the hard fails [88] and error-correction techniques can reduce the soft error rate to an acceptable level. Alternate technology choices such as thin SOI with or without a double gate could reduce soft errors through decreased collection volume and hard errors by eliminating (or reducing) the body doping.…”

Section: Sram Limitsmentioning

confidence: 99%

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Device scaling limits of Si MOSFETs and their application dependencies

et al. 2001

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This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metaloxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

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Section: Sram Limitsmentioning

confidence: 99%

Section: Sram Limitsmentioning

confidence: 99%

Device scaling limits of Si MOSFETs and their application dependencies

et al. 2001

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“…Domino logic is a high-performance circuit con guration that is usually embedded in static logic environment and tightly coupled with the clocking scheme. Domino CMOS has become the prevailing logic family for high performance CMOS applications and it is extensively used in the high speed processors [1][2][3][4][5][6] since they offer several advantages over static CMOS logic, namely higher speed, reduced transistor-count (resulting in reduced die area) and hazard-free operation.…”

Section: Introductionmentioning

confidence: 99%

“…This type of logic operates in two different phase of "precharge" and "evaluate". Compared to simple static CMOS NOR, dynamic domino logic achieves higher speed at the cost of higher power consumption [1][2][3][4][5][6]. However A major limitation in the single-rail Domino logic is that only non-inverting logic can be implemented.…”

Section: Introductionmentioning

confidence: 99%

An ultra-low-voltage, semi-floating-gate, domino, dual-rail, NOR gate

Dadashi

Mirmotahari

Berg

2015

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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In this paper, a new ultra low voltage (ULV) dualrail NOR gate based on the semi-floating-gate (SFG) structure is presented. Higher speed in the lower supply voltages and robustness against process variations, are the main advantages of the proposed approach in comparison to the previously reported domino dual-rail NOR gate. The simulation results in a typical TSMC 90nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.

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“…Domino logic circuits [1] are extensively used in high performance microprocessors [2][3][4][5][6] since they offer several advantages over static CMOS logic, namely higher speed, reduced transistor-count (resulting in reduced die area) and hazard-free operation. However, with technology scaling, designers find it difficult to deploy dynamic logic [7] because it has an increased susceptibility to switch failure (i.e.…”

Section: Introductionmentioning

confidence: 99%