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Transient Liquid Phase (TPL) bounding of Sn foil sandwiched between two Cu foils involves, in the temperature range above the melting point of Sn (232°C) and below 350°C, the formation and the growth of two intermetallic compounds (IMCs) Cu6Sn5 and Cu3Sn and mostly unintended micro-pores. The present study aims to analyze the mechanism of void development during the soldering process through an experimental and modeling approach of diffusion controlled IMC transformation. This modeling couples the diffusion process and the interface motion with the volume shrinkage induced by the difference of partial molar volumes of atoms between each phase. We also consider two types of interdiffusion transports: i) inter-diffusion based on the exchange of Cu and Sn-atoms and ii) inter-diffusion of Sn atoms with vacancies allowing Kirkendall void formation. The simulations of IMC growth performed corresponds to a sequence of planar phase layers, where the distinctive scallop morphology of the Cu6Sn5 layer is described through an analytical function allowing to quantify the grain boundary diffusion pathway. We take into account of the volume diffusion mechanism for Cu3Sn intermetallic.For Cu6Sn5 intermetallic two mechanisms are considered, volume diffusion and grain boundary diffusion, limited by grain growth. The simulations of IMC growth kinetics, for different transport scenarios, are compared to the experimental evolving morphologies to determine the most likely mechanism of micro-void formation.

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The demand for more efficient, cheaper, and smarter lighting system is ever increasing. Today it is well accepted that solid state lighting using high brightness LEDs is the leading technology for these lighting applications. LEDs has established itself as the solution for a large variety of applications such as street lighting, households, professional buildings etc… The growing need and incredible market for such lighting system drive the research for solutions on the cutting edge of the technology. However if the effectiveness of 2D GaN devices does not need to be proven any more, some reliability issues may arise due to difficult thermal management, proper encapsulation, good color control. Indeed one of the leading factor to improve LEDs devices as well as to reduce the price is to work on the packaging. How the interconnections or encapsulations are achieved, how the color conversion is done, or how is the heat generated handled. The main technology for LEDs fabrication is the growth of 2D GaN over sapphire substrates. Today some of the most widely spread configurations for these 2D LEDs are common chips (CC) and vertical thin film chips (VTF). In both cases the electrical contact is achieved by gold wires and in this configuration, in addition of the wire bonding step, the useful area for light emission is decreased because of the shadowing made by the metallic grid and the bonding pad surfaces. The flip chip (FC) configuration is also available in the LED manufacturing and looks promising as it achieves smaller size package and higher current. However, in this configuration the process remains complicate, as it needs an additional step for removing this growing substrate, the main technique today consisting on the Laser Lift Off (LLO). In this paper we present a novel approach to achieve promising LED devices. The new packaging approach uses the fabrication of nanowires over a silicon substrate, and some wafer level packaging to achieve the wires encapsulation and fabricate the P and N interconnections, using Through Silicon Vias (TSV). The silicon wafer level fabrication process achieves the possibility to use standard microelectronic equipment for the LED fabrication and its packaging. For this device specific silicon technologies are developed, such as wafer bonding and thinning, high aspect ratio TSV-last. Once fabricated the chip LEDs are diced and mounted on a specifically designed QFN which is itself directly mounted on a luminaire. The specific QFN is designed to achieve simultaneous reflow of many LEDs chips, and to properly handle the thermal management over the lifetime of the device. For test purposes and to characterize the electro-optical performances as well as some thermal resistances the LEDs are also mounted on a starboard. This new fabrication and packaging approach looks promising, and the specific technologies developed as well as the main characterization results will be presented.

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A new surface mount power package is introduced in this paper. Today there is a great need for a true high power surface mount package. This power package was designed from the start with surface mountlng in mind. Thus it is suitable for aU reflow soldering methods. The main advantages of the package are excellent thermal performance, high power capability and high power density, versatility, thermal efndent and reliable soldering. This paper will show that the new PowerSO-10 TM is a perfect successor of the well-known TO-220 package for the SMT envlronment.

Board level solder joint reliability is a critical issue for Quad Flat Non-lead Package (QFN), a type of leadframe CSP, during the thermal cycling test. However, currently there are very few papers available on fatigue modeling and thermal cycling test of QFN on board. In this paper, a parametric 3D FEA sliced model is built for QFN (4x4, 5x5, 6x6, 7x7, and 8x8) and PowerQFN-8x8 on board with considerations of detailed pad design, realistic shape of solder joint and solder fillet, and non-linear material properties. It has the capability to predict the fatigue life of solder joint during the thermal cycling test.The fatigue model applied is based on Darveaux's approach with non-linear viscoplastic, analysis of solder joints. Solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during the thermal cycling test. Higher SED leads to shorter fatigue life. For the test vehicles studied, the maximum SED is observed mostly at the top comer of peripheral solder joint. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified Darveaux correlation constants.Subsequently, design analysis is performed to study the effect of key package parameters such as die size, die pad size, lead size, land size, PCB thickness, solder standoff, with and without solder fillet, amount of soldering at the center pad, mold compound material properties, and thermal cycling temperature range. Generally, smaller die size, bigger pad size, thinner PCB, higher mold compound CTE, higher solder standoff, and extra soldering at the center pad help to enhance the fatigue life. Another enhanced QFN design with better solder joint reliability, PowerQFN, is also studied. 0-7803-7430-4/02/$17.00 02002 IEEE