Comprehensive design analysis of QFN and PowerQFN packages for enhanced board level solder joint reliability

Abstract

Board level solder joint reliability is a critical issue for Quad Flat Non-lead Package (QFN), a type of leadframe CSP, during the thermal cycling test. However, currently there are very few papers available on fatigue modeling and thermal cycling test of QFN on board. In this paper, a parametric 3D FEA sliced model is built for QFN (4x4, 5x5, 6x6, 7x7, and 8x8) and PowerQFN-8x8 on board with considerations of detailed pad design, realistic shape of solder joint and solder fillet, and non-linear material properties. It has the capability to predict the fatigue life of solder joint during the thermal cycling test.The fatigue model applied is based on Darveaux's approach with non-linear viscoplastic, analysis of solder joints. Solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during the thermal cycling test. Higher SED leads to shorter fatigue life. For the test vehicles studied, the maximum SED is observed mostly at the top comer of peripheral solder joint. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified Darveaux correlation constants.Subsequently, design analysis is performed to study the effect of key package parameters such as die size, die pad size, lead size, land size, PCB thickness, solder standoff, with and without solder fillet, amount of soldering at the center pad, mold compound material properties, and thermal cycling temperature range. Generally, smaller die size, bigger pad size, thinner PCB, higher mold compound CTE, higher solder standoff, and extra soldering at the center pad help to enhance the fatigue life. Another enhanced QFN design with better solder joint reliability, PowerQFN, is also studied. 0-7803-7430-4/02/$17.00 02002 IEEE

Internal Bump Cracking Risk Assessment for Flip Chip Ball Grid Array Package During Board Level Reliability Test Through Finite Element Analysis

“…Finite element modeling has been widely used to access solder joint reliability during board-level reliability tests [4][5][6][7][8]. The common approach is to generate the package global model with thermal load added and extract plastic work density increment from critical solder joints.…”