New Wafer Level Packaging Concept for Power LEDS

Abstract

The demand for more efficient, cheaper, and smarter lighting system is ever increasing. Today it is well accepted that solid state lighting using high brightness LEDs is the leading technology for these lighting applications. LEDs has established itself as the solution for a large variety of applications such as street lighting, households, professional buildings etc… The growing need and incredible market for such lighting system drive the research for solutions on the cutting edge of the technology. However if the effectiveness of 2D GaN devices does not need to be proven any more, some reliability issues may arise due to difficult thermal management, proper encapsulation, good color control. Indeed one of the leading factor to improve LEDs devices as well as to reduce the price is to work on the packaging. How the interconnections or encapsulations are achieved, how the color conversion is done, or how is the heat generated handled. The main technology for LEDs fabrication is the growth of 2D GaN over sapphire substrates. Today some of the most widely spread configurations for these 2D LEDs are common chips (CC) and vertical thin film chips (VTF). In both cases the electrical contact is achieved by gold wires and in this configuration, in addition of the wire bonding step, the useful area for light emission is decreased because of the shadowing made by the metallic grid and the bonding pad surfaces. The flip chip (FC) configuration is also available in the LED manufacturing and looks promising as it achieves smaller size package and higher current. However, in this configuration the process remains complicate, as it needs an additional step for removing this growing substrate, the main technique today consisting on the Laser Lift Off (LLO). In this paper we present a novel approach to achieve promising LED devices. The new packaging approach uses the fabrication of nanowires over a silicon substrate, and some wafer level packaging to achieve the wires encapsulation and fabricate the P and N interconnections, using Through Silicon Vias (TSV). The silicon wafer level fabrication process achieves the possibility to use standard microelectronic equipment for the LED fabrication and its packaging. For this device specific silicon technologies are developed, such as wafer bonding and thinning, high aspect ratio TSV-last. Once fabricated the chip LEDs are diced and mounted on a specifically designed QFN which is itself directly mounted on a luminaire. The specific QFN is designed to achieve simultaneous reflow of many LEDs chips, and to properly handle the thermal management over the lifetime of the device. For test purposes and to characterize the electro-optical performances as well as some thermal resistances the LEDs are also mounted on a starboard. This new fabrication and packaging approach looks promising, and the specific technologies developed as well as the main characterization results will be presented.