Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to <10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The first low BPD technique employs a selective etch of the substrate prior to epilayer growth to create a near on-axis surface where BPDs intersect the substrate surface. The second low BPD technique employs lithographic and dry etch patterning of the substrate prior to epilayer growth. Both processes impede the propagation of BPDs into epilayers by preferentially converting BPDs into threading edge dislocations (TEDs) during the initial stages of epilayer growth. With these techniques, we routinely achieve Vf stability yields of up to 90% in devices with active areas from 0.006 to 1 cm2, implying that the utility of the processes is not limited by device size.

Reactive ion etched silicon carbide mesa pin diodes with voltage blocking capabilities as high as 4.5 kV have been fabricated from 6H–SiC epitaxial layers. The epitaxial structure was grown by chemical vapor deposition on an n+ substrate giving a low-doped 45 μm thick n− active base layer and a 1.5 μm thick high-doped p+ emitter layer on top. A high minority carrier lifetime of 0.43 μs in the n− active base layer provides good on-state properties with a typical forward voltage drop of 6 V at 100 A/cm2.

High-voltage Schottky barrier diodes with low reverse leakage current were processed on hot-wall chemical vapor deposition grown 4H-SiC films. A metal overlap onto the oxide layer was employed to reduce electric field crowding at the contact periphery. By utilizing a 42–47 μm thick, high-quality epitaxial layers with doping in the range of 7×1014–2×1015 cm−3, a record blocking voltage of above 3 kV was achieved. The large diodes with 1.0 mm diameter showed breakdown at 2.1 kV. The reverse leakage current density at 1.0 kV was measured to be 7.0×10−7 A cm−2. Specific on-resistance of the diode with breakdown voltage at 3 kV was 34 mΩ cm2.

The recent discovery of forward-voltage degradation in SiC pin diodes has created an obstacle to the successful commercialization of SiC bipolar power devices. Accordingly, it has attracted intense interest around the world. This article summarizes the progress in both the fundamental understanding of the problem and its elimination. The degradation is due to the formation of Shockley-type stacking faults in the drift layer, which occurs through glide of bounding partial dislocations. The faults gradually cover the diode area, impeding current flow. Since the minimization of stress in the device structure could not prevent this phenomenon, its driving force appears to be intrinsic to the material. Stable devices can be fabricated by eliminating the nucleation sites, namely, dissociated basal-plane dislocations in the drift layer. Their density can be reduced by the conversion of basal-plane dislocations propagating from the substrate into threading dislocations during homoepitaxy.

International audience4H-SiC JBS diodes have been manufactured on a Norstel epitaxied N/N+ substrate using a JTE as edge termination. A breakdown voltage higher than 3.5 kV has been measured on 0.16 and 2.56 mm2 diodes. The leakage current in the 25°C-300°C temperature range depends on the bipolar/Schottky ratio whereas in forward mode its impact is minor. Diodes have been stressed in DC mode to show that the 2.56 mm2 diodes have a slight forward voltage degradation independently of the layout. In switching mode, the recovery charge is only 20 nC for a 4A current switched at 300°C

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