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The electrical performance of SiC-based microelectronic devices is strongly affected by the densities of interfacial traps introduced by the chemical and structural changes at the SiO2∕SiC interface during processing. We analyzed the structure and chemistry of this interface for the thermally grown SiO2∕4H-SiC heterostructure using high-resolution transmission electron microscopy (TEM), Z-contrast scanning TEM, and spatially resolved electron energy-loss spectroscopy. The analyses revealed the presence of distinct layers, several nanometers thick, on each side of the interface; additionally, partial amorphization of the top SiC surface was observed. These interfacial layers were attributed to the formation of a ternary Si–C–O phase during thermal oxidation.

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A method to form SiO2/SiC metal–oxide–semiconductor structures by oxidation of a thin polycrystalline silicon (polysilicon) layer deposited on SiC is demonstrated. The oxidation time used is sufficient to oxidize all the polysilicon while short enough at 1050 °C to insure insignificant oxidation of the underlying SiC. Since the oxidation of SiC is highly anisotropic, this method allows uniform oxide formation on a nonplanar SiC surface. The SiO2/SiC interface quality is comparable to that obtained with thermal oxidation.

Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to <10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The first low BPD technique employs a selective etch of the substrate prior to epilayer growth to create a near on-axis surface where BPDs intersect the substrate surface. The second low BPD technique employs lithographic and dry etch patterning of the substrate prior to epilayer growth. Both processes impede the propagation of BPDs into epilayers by preferentially converting BPDs into threading edge dislocations (TEDs) during the initial stages of epilayer growth. With these techniques, we routinely achieve Vf stability yields of up to 90% in devices with active areas from 0.006 to 1 cm2, implying that the utility of the processes is not limited by device size.

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The driving force of stacking-fault expansion in SiC p-i-n diodes was investigated using optical emission microscopy and transmission electron microscopy. The stacking-fault expansion and properties of the partial dislocations were inconsistent with any stress as the driving force. A thermodynamic free energy difference between the perfect and a faulted structure is suggested as a plausible driving force in the tested diodes, indicating that hexagonal polytypes of silicon carbide are metastable at room temperature.

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