No abstract

No abstract

We use the high–low capacitance–voltage technique and the conductance–frequency techniques to characterize the SiO2/SiC interface formed by thermal oxidation of the silicon-face (0001) c-axis, the (112̄0) a-axis, and the (11̄00) a-axis orientations of 6H–SiC. The oxidation rate of the a-axis orientations is 3–5 times higher than that of the silicon face. Interface state densities on the a-axis orientations are a factor of 4–10 times higher than the Si-face c-axis orientation for both n-type and p-type dopings. Maximum oxide electric breakdown fields are about 10–11 MV/cm for both a-axis and c-axis orientations for an oxide thickness of about 60 nm.

The 4H polytype of silicon carbide (SiC) has a wider band gap and higher electron mobility than either the 6H or 3C polytypes. We show here that similar oxidation rates and interfacial quality can be obtained on 4H-SiC and 6H-SiC by thermal oxidation. This makes the 4H polytype an attractive choice for developing SiC power metal–oxide–semiconductor field effect transistors. Postoxidation annealing in helium increases fixed charge and interface state densities in both 4H and 6H metal–oxide–semiconductor capacitors.

Thermal processing of polycrystalline silicon (polysilicon)/SiO2/SiC metal-oxide-semiconductor (MOS) devices following polysilicon deposition can have an adverse effect on the electrical properties of the SiO2/SiC interface. The primary effect is a negative shift in flatband voltage caused by an increase in fixed oxide charge and interface state density. These effects can be minimized or eliminated by restricting processing temperatures to 900 °C or below following polysilicon gate deposition.