It is found that 0.1 V-order threshold voltage shift (Vth shift) takes place in polycrystalline-silicon thin film transistors during negative-bias temperature stress (−BT stress), while the Vth shift in the case of positive-bias temperature stress is negligibly small. The Vth shift caused by −BT stress has an exponential dependence on the stress gate bias and reciprocal of temperature. Moreover, it also has a close relation with the grain size of poly-Si films and the hydrogenation process. However, it is independent of the gate insulator materials. Some models previously proposed for amorphous silicon TFTs could not explain these results. A new model is proposed based on a reaction between hydrogen and the SiO2 network at and near the poly-Si/SiO2 interface to clarify the mechanism and for consistent interpretation of the experimental results. Furthermore, the model has been verified qualitatively.
Silicon-surface microroughness was formed by cleaning cycles of an NH4OH-H2O2-H2O solution. Not only the roughness of the silicon surface, but also the roughness of the thermally oxidized surface and that of the surface after the removal of the thermal oxide (corresponding to the Si/SiO2 interface roughness) were observed by means of atomic-force microscopy. By using metal-oxide-semiconductor structured samples, investigations were conducted of the electrical properties induced by surface microroughness, such as the oxide-trapped charges, Si/SiO2 interface states, neutral oxide-trap centers, and oxide-breakdown characteristics. As a result, it was clarified that the neutral oxide traps, as well as the Si/SiO2-interface states, apparently increase in spite of only a small change in roughness. It was also verified, however, that the oxide-trapped charges and the oxide breakdown do not change over the scale of roughness change in the present experiments, if contaminants were carefully eliminated from the Si surface.
The computer simulations of the time dependent dielectric breakdown (TDDB) percolation path are performed for ultrathin gate oxides. With our new percolation model, an interesting and new behavior of TDDB distribution was found. Weibull slope decreases monotonously with decreasing oxide thickness, and has a gap at an oxide thickness of approximately the effective defect size. This behavior can be understood well if we consider that an overlap of two neighboring defects becomes necessary to cause a sudden breakdown when oxide thickness exceeds the effective defect size. This phenomenon is very important because Weibull slope has a large effect on device reliability.
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