Mechanism of negative-bias temperature instability in polycrystalline-silicon thin film transistors

Abstract

It is found that 0.1 V-order threshold voltage shift (Vth shift) takes place in polycrystalline-silicon thin film transistors during negative-bias temperature stress (−BT stress), while the Vth shift in the case of positive-bias temperature stress is negligibly small. The Vth shift caused by −BT stress has an exponential dependence on the stress gate bias and reciprocal of temperature. Moreover, it also has a close relation with the grain size of poly-Si films and the hydrogenation process. However, it is independent of the gate insulator materials. Some models previously proposed for amorphous silicon TFTs could not explain these results. A new model is proposed based on a reaction between hydrogen and the SiO2 network at and near the poly-Si/SiO2 interface to clarify the mechanism and for consistent interpretation of the experimental results. Furthermore, the model has been verified qualitatively.

Two-Stage Degradation of p-Type Polycrystalline Silicon Thin-Film Transistors Under Dynamic Positive Bias Temperature Stress

“…At low-stress temperature range (20°C-60°C), the I ON increase in the first degradation stage is suppressed at higher stress temperatures. It is within expectation because at higher temperatures the outemission of the trapped electrons from the gate oxide is enhanced [15], [24], suppressing the first-stage degradation. Along with the suppression of the first-stage degradation, the second-stage degradation occurs within a shorter stress time at higher stress temperatures, because the I ON drop in the second-stage easily overwhelms the limited I ON increase of the first stage.…”

“…Various stress conditions, such as gate or drain bias, dc or pulsed bias, have been performed on n-type poly-Si TFTs to study their instability issues [7]- [14]. For p-type poly-Si TFTs, both static and dynamic negative bias temperature instability have been extensively investigated [15]- [19]. In TFT-based circuits, positive bias temperature instability (PBTI) of p-type poly-Si TFTs is also an important concern.…”

Electrical Stability and Flicker Noise of Thin-Film Heterojunction FETs on Poly-Si Substrates

“…For applications with large dynamic range requirements, larger swings can be obtained with circuit techniques [21]. The ON/OFF ratio [4]), and (c) V T of p-channel large-grain and small-grain poly-Si TFTs reported in [24], with drain and source terminals grounded during bias stress. (d) Stability of normalized drain current in saturation for small-grain poly-Si HJFETs (this work) and a-Si:H TFTs with gate nitride deposition temperature of 200 • C [35] and 300 • C [35], [36] at typical drive conditions for 1000 Cd/m 2 OLED brightness (starting I D ≈ 5 µA).…”

Defect generation in non-nitrided and nitrided sputtered gate oxides under post-irradiation Fowler–Nordheim constant current stress

“…Using MOS structures gives also an opportunity for a fast evaluation of near border traps in deposited oxide, defects that are largely overlooked in studies of stability of TFTs. Creation of grain boundary traps are documented in electrically stressed TFTs [8,9] and it is anticipated that they should be also generated if TFTs were exposed to irradiation.…”