In the last years an increasing number of mobile electronic products was launched to the market like mobile communicators, combining the RF fimctions of a mobile phone and the complexity of a palm top computer. Inside these devices there is less and less space for the electronic system while packaging density and operating frequencies are constantly increasing. Additionally the product life time is going down, requiring short design cycles and a production at low-cost based on well established technologies. These trends are a strong challenge for microelectronic packaging and assembly technology.An advanced packaging concept will be presented, the Chip in Polymer technology, which aims to face the above mentioned challenges. It is based on the embedding of ultra thin semiconductor chips into the build-up layers of printed circuit boards together with integrated passive components.Processing issues with regard to registration tolerances between embedded chips an metal lines will be discussed. First results of the formation of integrated resistors will be shown, using electrolessly deposited NIP layers. The embedding technology will put into relation to common interconnection technologies regarding expected RF properties and system design aspects. Basic thermomechanical properties of a first technology demonstrator, a stackable chip scale package, will be discussed using finite element modeling.
Simple adhesion tests like the pull-out test or the button shear tests have been used in industry for decades. They offer a great potential for comparison of different molding compounds, encapsulants, or adhesives on different types of sub-strates with or without surface treatment. However, for theoretical prediction purposes, interface fracture mechanics parameters are needed. Quantitative evaluations of the test applied to molding compound (MC)-button on Cu-leadframe by different fracture- and damage mechanical approaches are the subjects of the paper. Defect tolerant methodologies like the "virtual crack closure technique" (VCCT), which consider the interface initially delaminated, are compared to the damage methodology "cohesive zone modelling (CZM)", which needs no initial crack and can track the delamination progress. Calculated fracture parameters, in particular the energy release rates and mode mixity are compared. Effects on these parameters are discussed for d ifferent button shapes. In-situ tracking of delamination progress for a cubic button is shown using the optical correlation technique microDAC
The technology of surface acoustic wave (SAW) devices allows the integration of signal processing and sensor functions within one product. In the past, SAW sensors have been operated at room temperature or 100 to 200°C at most. Materials related problems become obvious if one attempts to increase this operating temperature to a value as high as 1000°C. First experimental results will be presented based on a variation of the metallization and the use of diffusion barriers. It is expected that the use of these specially taylored materials with particular functional properties will lead to a considerable improvement of the lifetime and reliability of SAW sensors and the development of devices resistant to high temperatures as well as high pressures and chemically aggressive environments. The high-temperature characteristics of such novel devices are investigated by finite element simulation and by experimental deformation analyses. It will also be discussed which assembly, interconnection, and packaging techniques are applicable at 1000°C.
The application of copper-TSVs for 3D-IC-integration generates novel challenges for reliability analysis and prediction, i.e. to master multiple failure criteria for combined loading including residual stresses, interface delamination, cracking and fatigue. So, the thermal expansion mismatch between copper and silicon yields to stress situation in silicon surrounding the TSVs which is influencing the electron mobility and as a result the transient behavior of transistors. Furthermore, pumping and protrusion of copper is a challenge for Back-end of Line (BEoL) layers of advanced CMOS technologies already during manufacturing. These effects depend highly on the temperature dependent elastic-plastic behavior of TSV-copper and the residual stresses determined by the electro deposition chemistry and annealing conditions
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