This paper investigates the thermo-mechanical reliability of inter-chip-vias (ICV) for 3D chip stacking after processing and under external thermal loads relevant for the envisaged field of application (mobile, automotive) by Finite Element simulation. First the materials are characterised by nano-indentation to determine elasto-plastic data. Finite Element simulations are used to reproduce these data and to extract local material properties like E-modulus and yield stress. Accumulated plastic strain is used as failure indicator under periodic thermal loading of an ICV. Geometrical, material and process-related parameters are varied to obtain first design guidelines for this new technology. The locations of stress and strain accumulation are given.
The 3D-packaging technology makes it possible to stack the PCBs on top of each other and thus make full use of the third dimension. A unique space between the stacked PCB layers enables a reproducible technology without shortcuts or unconnected bumps. New applications in 3D-PDB-packages, called PCBMEMS can be realized with the combination of electric bumps and solder rings. The paper shows an fluidic cooled 11-PCB-layer with high power components. Water channels in the PCB-package dissipate the heat from the inside of the package to the environment. Heat dissipation is a bigger challenge for stacks of 3D-packages than for normal printed circuit boards (PCBs). This research paper investigates some design suggestions for a better heat dissipation. On the basis of this research paper, it becomes possible to choose the best suited PCB design. The experimental results were compared to thermal simulation results. The results of the measurements and FEM simulations show, how important it is to combine the electrical and geometrical functions of 3D packages with a thermally optimized PCB design. A better heat spreading and conduction in a 3D package makes the stack more reliable at higher power dissipation.
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