Integration of passive and active components into build-up layers

Ostmann, A.; Neumann, Alexander; Auersperg, J.; Ghahremani, C.; Sommer, Grit; Aschenbrenner, R.; Reichl, H.

doi:10.1109/eptc.2002.1185672

Cited by 20 publications

(8 citation statements)

References 4 publications

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“…The ultrathin semiconductor chips were embedded into the build-up layers of PCB together with integrated passive components. Electrical interconnection between chip and outer layer footprints were realized by laser-drilled and metallized microvias [32]- [34]. The detailed packaging process is shown in Fig.…”

Section: Chip Embedded Packaging Scheme 1) Ceramic Embedded Power mentioning

confidence: 99%

Review of Packaging Schemes for Power Module

Hou

Wang²,

Cao

et al. 2020

IEEE J. Emerg. Sel. Topics Power Electron.

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SiC devices are promising for outperforming Si counterparts in high-frequency applications due to its superior material properties. Conventional wirebonded packaging scheme has been one of the most preferred package structures for power modules. However, the technique limits the performance of a SiC power module due to parasitic inductance and heat dissipation issues that are inherent with aluminum wires. In this article, low parasitic inductance and high-efficient cooling interconnection techniques for Si power modules, which are the foundation of packaging methods of SiC ones, are reviewed first. Then, attempts on developing packaging techniques for SiC power modules are thoroughly overviewed. Finally, scientific challenges in the packaging of SiC power module are summarized.

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Section: Chip Embedded Packaging Scheme 1) Ceramic Embedded Power mentioning

confidence: 99%

Review of Packaging Schemes for Power Module

Hou

Wang²,

Cao

et al. 2020

IEEE J. Emerg. Sel. Topics Power Electron.

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show abstract

“…Hence, metallization layers of front-side pads on these devices are Al, which is not compatible with PCB-embedded package and an additional metallization layer is required on the front-side source and gate pads [17], [32]. Dies that had extra metallization layers are then embedded in the PCB, followed by blind vias that are usually formed by laser drilling and Cu plating, thus realizing the interconnection between dies and outer layers [14], [18], [19], [22]. However, if energy is not properly controlled, the terminal metallization pads could be damaged by laser drilling.…”

Section: A Pid Exposure and Development Techniquementioning

confidence: 99%

“…The ultrathin semiconductor chips were embedded into the build-up layers of PCB together with integrated passive components. Electrical interconnection between chip and outer-layer footprints were realized by laserdrilled and metallized microvias [14]- [16].…”

Section: Introductionmentioning

confidence: 99%

Fan-Out Panel-Level PCB-Embedded SiC Power MOSFETs Packaging

Hou

Wang²,

Chen

et al. 2020

IEEE J. Emerg. Sel. Topics Power Electron.

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In this article, a novel fan-out panel-level printed circuit board (PCB)-embedded package for phase-leg silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power module is presented. Electro-thermomechanical co-design was conducted, and the maximum package parasitic inductance was found to be about 1.24 nH at 100 kHz. Compared with wire-bonded packages, the parasitic inductances of the PCB-embedded package decreased at least by 87.6%. Compared with blind via structure, the thermal resistance of the proposed blind block structure reduced at most by about 26%, and the stress of the SiC MOSFETs decreased by about 45.2%. Then, a novel PCB-embedded packaging process was developed, and three key packaging processes were analyzed. Furthermore, effect of PCB-embedded package on static characterization of SiC MOSFET was analyzed, and it was found that: 1) Output current of PCB-embedded package was decreased under a certain gate-source voltage compared to SiC die; 2) Miller capacitance of SiC MOSFET was increased thanks to parasitic capacitance induced by package; and 3) compared with SiC die, nonflat miller plateau of the PCB-embedded package extends, and as drain-source voltage increases, the nonflat miller plateau extends. Lastly, switching characteristics of the PCB-embedded package and TO-247 package were compared. The results show that the PCB-embedded package has smaller parasitic inductances.

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“…Another stacking approach for SIP and SOP generation was presented by Ostmann et al [9], [10] (Fig. 1) and will be described in detail later.…”

Section: B Volume Processes For Sip/sop Generationmentioning

confidence: 99%

Stackable system-on-packages with integrated components

Becker

Jung

Ostmann

et al. 2004

IEEE Trans. Adv. Packag.

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In recent years, an increasing number of mobile electronic products such as mobile communicators, combining the functions of a mobile phone and a PDA are beginning to emerge. These devices are highly miniaturized and yet provide a variety of functions at ever higher speeds. Additionally, the product cycle time is getting faster, requiring short design and production cycles at ever lower cost. These trends are posing great set of challenges for the microelectronics and packaging and assembly industry. There seem to be two approaches to solve these challenges-system-in-package (SIP) by stacking of packaged integrated circuits (ICs) or system-on-package (SOP) by stacking of packages with embedded active and passive components. The buried components in SOP require significantly less space in z direction, thereby allowing the formation of three-dimensional (3-D) stackable packages. In this paper, two approaches for stacking SOPs were presented, the so-called chip-in-polymer (CIP) technology and duromer molded interconnect device (MID)/WLP technology.Index Terms-Embedded passives, modular systems, molded interconnect device (MID), packaging, system-on-package (SOP).

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Integration of passive and active components into build-up layers

Cited by 20 publications

References 4 publications

Review of Packaging Schemes for Power Module

Review of Packaging Schemes for Power Module

Fan-Out Panel-Level PCB-Embedded SiC Power MOSFETs Packaging

Stackable system-on-packages with integrated components

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