Stackable system-on-packages with integrated components

Abstract

In recent years, an increasing number of mobile electronic products such as mobile communicators, combining the functions of a mobile phone and a PDA are beginning to emerge. These devices are highly miniaturized and yet provide a variety of functions at ever higher speeds. Additionally, the product cycle time is getting faster, requiring short design and production cycles at ever lower cost. These trends are posing great set of challenges for the microelectronics and packaging and assembly industry. There seem to be two approaches to solve these challenges-system-in-package (SIP) by stacking of packaged integrated circuits (ICs) or system-on-package (SOP) by stacking of packages with embedded active and passive components. The buried components in SOP require significantly less space in z direction, thereby allowing the formation of three-dimensional (3-D) stackable packages. In this paper, two approaches for stacking SOPs were presented, the so-called chip-in-polymer (CIP) technology and duromer molded interconnect device (MID)/WLP technology.Index Terms-Embedded passives, modular systems, molded interconnect device (MID), packaging, system-on-package (SOP).

Encapsulation Process Technology

“…An encapsulation technique specifi c to 3D packaging is the chip-inpolymer (CIP) [33]. Figure 3.35 shows the process fl ow for a CIP package.…”

Duromer MID technology for system-in-package generation

“…A schematic is given in Fig. 1: The routing on package level is realized by a metallized and structured encapsulant-the Duromer MID approach, combining lowest coefficient of thermal expansion (CTE) encapsulantsanddirect metallization processes with plated through holes [2]. Compared to the use of an additional interposer as found with state-of-the-art 3-D stackable packages, a reduction of interconnection layers is achieved leading to increased package reliability.…”

“…Applications range from optical sensor packages 1 to automotive electric and home appliance products. 2 With Duromer MID basically the same applications can be realized, but due to the superior thermomechanical matching of duromers to electronic components, it has the potential for direct IC and component embedding and to provide additional functionality to the component(s) packaged as described above. This additional functionality gives Duromer MID the potential not only for the realization of single IC packages, but also for system-in-package (SiP)/system-on-package (SoP) generation.…”

Thermal and Electrical Performance Enhancement with a Cost-Effective Packaging for High Speed Memory Chips

“…On the other hands, an emerging technology of embedded actives [5][6], in which active chips are embedded in dielectric layers inside substrates, has shown its potential benefits of cost-down in memory chip packaging because of its PCB-like interconnections and processes. A type I chip-in-substrate package (CiSP), as shown in Fig.…”