SiC devices are promising for outperforming Si counterparts in high-frequency applications due to its superior material properties. Conventional wirebonded packaging scheme has been one of the most preferred package structures for power modules. However, the technique limits the performance of a SiC power module due to parasitic inductance and heat dissipation issues that are inherent with aluminum wires. In this article, low parasitic inductance and high-efficient cooling interconnection techniques for Si power modules, which are the foundation of packaging methods of SiC ones, are reviewed first. Then, attempts on developing packaging techniques for SiC power modules are thoroughly overviewed. Finally, scientific challenges in the packaging of SiC power module are summarized.
A new panel-level silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) power module was developed by using the fan-out and embedded chip technologies. To achieve the more effective thermal management and higher reliability under thermal cycling, a new optimization method called Ant colony optimization-back propagation neural network (ACO-BPNN) was developed for optimizing SiC modules, and contrast it with the Response Surface Method (RSM). First, the heat dissipations of SiC MOSFET with different redistribution layer (RDL) materials were simulated through the ANSYS finite element simulation. Then, the RSM was adopted to design the experiments for optimization. Third, the optimized design considering both junction temperature and thermal-mechanical stress is obtained using RSM and ACO-BPNN. The results show that: 1) compared with nanosilver, copper has a relatively good heat dissipation effect, but nano-silver has a better thermodynamic performance, and 2) ACO-BPNN can provide more accurate optimization Manuscript
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