Fan-Out Panel-Level PCB-Embedded SiC Power MOSFETs Packaging

Abstract

In this article, a novel fan-out panel-level printed circuit board (PCB)-embedded package for phase-leg silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power module is presented. Electro-thermomechanical co-design was conducted, and the maximum package parasitic inductance was found to be about 1.24 nH at 100 kHz. Compared with wire-bonded packages, the parasitic inductances of the PCB-embedded package decreased at least by 87.6%. Compared with blind via structure, the thermal resistance of the proposed blind block structure reduced at most by about 26%, and the stress of the SiC MOSFETs decreased by about 45.2%. Then, a novel PCB-embedded packaging process was developed, and three key packaging processes were analyzed. Furthermore, effect of PCB-embedded package on static characterization of SiC MOSFET was analyzed, and it was found that: 1) Output current of PCB-embedded package was decreased under a certain gate-source voltage compared to SiC die; 2) Miller capacitance of SiC MOSFET was increased thanks to parasitic capacitance induced by package; and 3) compared with SiC die, nonflat miller plateau of the PCB-embedded package extends, and as drain-source voltage increases, the nonflat miller plateau extends. Lastly, switching characteristics of the PCB-embedded package and TO-247 package were compared. The results show that the PCB-embedded package has smaller parasitic inductances.

Design of a Fan-Out Panel-Level SiC MOSFET Power Module Using Ant Colony Optimization-Back Propagation Neural Network

“…We have described the MOSFET encapsulation process in detail in [20]. MOSFET packaging begins with producing a 0.18-mm core plate by compressing a 0.1-mm-thick layer of Bismaleimide-Triazine (BT) laminate, two 0.04-mm-thick layers of Bismaleimide-Triazine (BT) pre-preg, and two 3-μm-thick layers of copper foil under high temperature and pressure.…”

“…Referring to previous research [20], a 3-D model of the embedded fan-out SiC MOSFET power module was created, as shown in Fig. 3(a).…”

“…The internal thermal conduction structure of the package module has been described in detail in [20].…”

Automotive Power Module Packaging: Current Status and Future Trends

“…22, where the embedding of the devices is treated as a post-process after the laminate`s lay-up [106]. In addition, in [107], a fan-out process is investigated, which uses panel-level physical vapor deposition and redistribution layers technologies to achieve die attachments and interconnections.…”

Maleimide Resin Blends with Enhanced Toughness for High-Temperature Semiconductor Packaging

“…In recent years, researchers have developed power modules that use FOPLP or the technology that applied it, i.e., embedded die technology. [22][23][24][25][26][27] Glass-fiber-reinforced composites have also been used as a sheet molding material for power modules. [28,29] However, although these composites facilitate the control of panel warpage, they do not allow for effective impregnation with resin and make it challenging to produce thin packaging.…”