Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of intellectual property (IP) cores. Reducing power is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, we propose a reusable context pipelining (RCP) architecture to reduce power-overhead caused by reconfiguration. It shows that the power reduction can be achieved by using the characteristics of loop pipelining, which is a multiple instruction stream, multiple data stream (MIMD)-style execution model. RCP efficiently reduces power consumption in configuration cache without performance degradation. Experimental results show that the proposed approach saves much power even with reduced configuration cache size. Power reduction ratio in the configuration cache and the entire architecture are up to 86.33% and 37.19%, respectively, compared to the base architecture.Index Terms-Coarse-grained reconfigurable architecture, configuration cache, embedded system, loop pipelining, low power.
In this paper, an array antenna for LOS datalink for mounting UAV(Unmanned Aerial Vehicle) of low-probability of intercept is presented. For low RCS, radome was designed by conformal form, and other components were inserted into the UAV. The antenna of the transmitter and receiver are each composed of 12×12 array antennas, and include a beam steering function by controlling the phase of the unit element for the Uni-directional pattern and the Bi-directional pattern. As a result of the measurement of the manufactured antenna, it was confirmed that all the required specifications were met, and the installing possibility of the UAV platform on low-probability of intercept in the future was confirmed.
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