Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture

Kim, Yoonjin; Park, Ilhyun; Choi, Ki‐Young; Paek, Yunheung

doi:10.1145/1165573.1165646

Cited by 45 publications

(24 citation statements)

References 15 publications

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“…overview given in [1], the aspect of applying specially suited power reduction techniques on such architectures has not been covered in depth, so far. Often single figures and breakdowns of power consumption are given, like in [2] or [3], but no attempts were made to exploit architecture-specific features to reach a better power and energy efficiency, besides the configuration cache optimization given in [1]. In this work we combine the custom hierarchical and fine-grained automatic clock gating technique, see Section 3.2, and obtain a considerable increase in power efficiency for our case study CGRA.…”

Section: Related Workmentioning

confidence: 99%

Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures

Kissler

Strawetz

Hannig

et al. 2009

Journal of Low Power Electronics

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Abstract. Coarse-grained reconfigurable architectures deliver high performance and energy efficiency for computationally intensive applications like mobile multimedia and wireless communication. This paper deals with the aspect of power-efficient dynamic reconfiguration control techniques in such architectures. Proper clock domain partitioning with custom clock gating combined with automatic clock gating resulted in a 35% total power reduction. This is more than a threefold as compared to the single clock gating techniques applied separately. The corresponding case study application with 0.064 mW/MHz and 124 MOPS/mW power efficiency outperforms the major coarse-grained and general purpose embedded processor architectures by a factor of 1.7 to 28.

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Section: Related Workmentioning

confidence: 99%

Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures

Kissler

Strawetz

Hannig

et al. 2009

Journal of Low Power Electronics

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“…He described mapping problem as finding a subgraph in a minimally TimeExtended CGRA (TEC) graph, where the subgraph is Epimorphic to the input DFG. EPIMap was categorized into temporal mapping [3]. Operands in same stage were data independent and were not connected with each other.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual V<sub>DD</sub>

Yin

Liu

et al. 2015

IEICE Trans. Inf. & Syst.

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SUMMARYCoarse Grained Reconfigurable Architectures (CGRAs) are promising platform based on its high-performance and low cost. Researchers have developed efficient compilers for mapping computeintensive applications on CGRA using modulo scheduling. In order to generate loop kernel, every stage of kernel are forced to have the same execution time which is determined by the critical PE. Hence non-critical PEs can decrease the supply voltage according to its slack time. The variable Dual-V DD CGRA incorporates this feature to reduce power consumption. Previous work mainly focuses on calculating a global optimal V DDL using overall optimization method that does not fully exploit the flexibility of architecture. In this brief, we adopt variable optimal V DDL in each stage of kernel concerning their pattern respectively instead of the fixed simulated global optimal V DDL . Experiment shows our proposed heuristic approach could reduce the power by 27.6% on average without decreasing performance. The compilation time is also acceptable. key words: loop mapping, software pipelining, Dual-V DD , low power, Graph Minor

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“…The abundance of computation resources simply adds up the list for configurations to the control path. As a result, the total number of control bits to configure the whole array can reach nearly 1000 bits each cycle, and the control path takes up to 43% of the total power consumption in existing CGRA designs [3,2]. Moreover, control bits are read from the on-chip memory every cycle regardless of the array's utilization.…”

Section: Introductionmentioning

confidence: 99%

“…One exception is [3] wherein a hybrid configuration cache is proposed that utilizes the temporal mapping for control power reduction. Temporal mapping only utilizes a single column of PEs in the array to map the entire loop and the The execution of the loop is pipelined by running multiple iterations on different columns in the array.…”

Section: Introductionmentioning

confidence: 99%

A dataflow-centric approach to design low power control paths in CGRAs

Park

Mahlke

2009

2009 IEEE 7th Symposium on Application Specific Processors

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Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing high computation throughput, scalability, low cost, and energy efficiency, but suffer from relatively high control path power consumption. We take the concept of a token network from dataflow machines and apply it to the control path of CGRAs to increase efficiency. As a result, instruction memory power is reduced by 74% , the overall control path power by 56%, and the total system power by 25%.

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Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture

Cited by 45 publications

References 15 publications

Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures

Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures

Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual V<sub>DD</sub>

A dataflow-centric approach to design low power control paths in CGRAs

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