Power-Conscious Configuration Cache Structure and Code Mapping for Coarse-Grained Reconfigurable Architecture

Kim, Yoonjin; Park, Ilhyun; Choi, Ki‐Young; Paek, Yunheung

doi:10.1109/lpe.2006.4271855

Cited by 1 publication

(1 citation statement)

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“…Many reconfigurable architectures, including TRIPS [32,33], CGRA [34], and ADRES [37], have been proposed to accelerate the algorithm DFGs. However, they are not targeting at the stencil applications so that the data movement and reuse are not tuned for this neighboring access pattern.…”

Section: Cgra For Stencil Computationsmentioning

confidence: 99%

Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators

Inagaki

Takamaeda-Yamazaki

et al. 2014

2014 Second International Symposium on Computing and Networking

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The Energy-aware Multi-mode Accelerator eXtension [24,25] (EMAX) is equipped with distributed single-port local memories and ring-formed interconnections. The accelerator is designed to achieve extremely high throughput for scientific computations, big data, and image processing as well as low-power consumption. However, before mapping algorithms on the accelerator, application developers require sufficient knowledge of the hardware organization and specially designed instructions. They also need significant effort to tune the code for improving execution efficiency when no well-designed compiler or library is available. A similar problem exists in EMAX. To address this problem, we focus on library support for stencil (nearest-neighbor) computations that represent a class of algorithms commonly used in many partial differential equation (PDE) solvers. In this dissertation, we address the following topics: (1) system configuration, features, and mnemonics of EMAX; (2) instruction mapping techniques that reduce the amount of data to be read from the main memory; (3) performance evaluation of the library for PDE solvers. With the features of a library that can reuse the local data across the outer loop iterations and map many instructions by unrolling the outer loops, the amount of data to be read from the main memory is significantly reduced to a minimum of 1/7 compared with a hand-tuned code. In addition, the stencil library reduced the execution time 23% more than a general-purpose processor, and it was shown that EMAX and the 3D-Stencil Library have the superior performance compared with GPGPU.

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