Abstract. Emerging web applications like cloud computing, Big Data and social networks have created the need for powerful centres hosting hundreds of thousands of servers. Currently, the data centres are based on general purpose processors that provide high flexibility buts lack the energy e ciency of customized accelerators. VINEYARD aims to develop an integrated platform for energy-e cient data centres based on new servers with novel, coarse-grain and fine-grain, programmable hardware accelerators. It will, also, build a high-level programming framework for allowing end-users to seamlessly utilize these accelerators in heterogeneous computing systems by employing typical data-centre programming frameworks (e.g. MapReduce, Storm, Spark, etc.). This programming framework will, further, allow the hardware accelerators to be swapped in and out of the heterogeneous infrastructure so as to o↵er high flexibility and energy e ciency. VINEYARD will foster the expansion of the soft-IP core industry, currently limited in the embedded systems, to the data-centre market. VINEYARD plans to demonstrate the advantages of its approach in three real use-cases a) a bio-informatics application for high-accuracy brain modeling, b) two critical financial applications, and c) a big-data analysis application.

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Network-on-chip (NoC) is being proposed as a scalable and reusable communication platform for future SoC applications. An important problem in NoC design is deciding the type of routing which is one of the most crucial key factors that greatly affects the NoC architecture based systems performance. Currently, most of the proposals for routing in NoC are based upon deterministic routing mechanism because it gives better latency at low packet injection and requires less resources while guaranteeing an orderly packet arrival. However, the disadvantage of deterministic routing is that it cannot respond to dynamic network condition such as congestion. When the network becomes congested, adaptive routing provides better throughput and lower latency by allowing alternate paths. In this paper, using simulation, we evaluate the performance of adaptive routing algorithm to deterministic routing strategy respected to throughput, power consumption and latency. The simulation environment is 2D-Mesh based NoC topology including different kinds of mapping Video Object Plane Decoder (VOPD) application onto this architecture. The experiment results prove the adaptive routing performance under network congestion occurrence.

Emerging applications like cloud computing and big data analytics have created the need for powerful centers hosting hundreds of thousands of servers. Currently, the data centers are based on general purpose processors that provide high flexibility but lacks the energy efficiency of customized accelerators. VINEYARD 1 aims to develop novel servers based on programmable hardware accelerators. Furthermore, VINEYARD will develop an integrated framework for allowing end-users to seamlessly utilize these accelerators in heterogeneous computing systems by using typical data-center programming frameworks (i.e. Spark). VINEYARD will foster the expansion of the soft-IP cores industry, currently limited in the embedded systems, to the data center market. VINEYARD plans to demonstrate the advantages of its approach in three real use-cases a) a bio-informatics application for high-accuracy brain modeling, b) two critical financial applications and c) a big-data analysis application.

Abstract. Network-on-chip (NoC) is being proposed as a scalable and reusable communication platform for future SoC applications. The NoC, somewhat, resembles the parallel computer network. However, the NoC design highly requires the certain satisfaction of latency, power consumption, and area constraints. The latency of the network relates much to throughput and power consumption. Moreover, the IPs and the network are heterogeneous. Hence, a certain mapping of IPs onto a certain architecture produces a certain value of network latency as well as power consumption. The change of mapping scheme leads to a significant change of the values of these constraints. The fact that if we want to maximize the system's throughput, the network latency also increases and if we minimize the network latency, the trade off is that the throughput will decrease. In this paper, we present an mapping scheme that does compromise between throughput maximization and latency minimization. This sub-optimal mapping is found using the spanning tree searching algorithm. The experiment architecture using here is Mesh based topology. We use NS2 to simulate and calculate the system throughput and system power consumption is calculated using Orion model.