Realization of Video Object Plane Decoder on On-Chip Network Architecture

Nguyen, Huy-Nam; Ngo, Vu-Duc; Choi, Hae-Wook

doi:10.1007/11599555_26

Cited by 6 publications

(4 citation statements)

References 8 publications

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“…Pjlit f E clk (Earb + Exbar + Ebufr + EbufW) x5j (5) Ri where Ri is the route that flit i goes through and r 1=, if throuter C R (6) O, ot herwi'se Finally, the power consumption of total network is: In this paper, we simulate and analyze performance of NoC using deterministic and adaptive routings. With the results in Table.1, we can calculate the power consumption of the whole network.…”

Section: Power Analysis V Simulation Results and Discussionmentioning

confidence: 99%

“…With the results in Table.1, we can calculate the power consumption of the whole network. The authors in [6] compared the performances in term of throughput between random mapping and optimal mapping VOPD decoder onto Mesh network with different bisection bandwidths. The results presented that adaptive routing provides much higher throughput.…”

Section: Power Analysis V Simulation Results and Discussionmentioning

confidence: 99%

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Assessing Routing Behavior on On-Chip-Network

Nguyen¹,

Ngo²,

Choi³

2006

2006 International Conference on Computer Engineering and Systems

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Network-on-chip (NoC) is being proposed as a scalable and reusable communication platform for future SoC applications. An important problem in NoC design is deciding the type of routing which is one of the most crucial key factors that greatly affects the NoC architecture based systems performance. Currently, most of the proposals for routing in NoC are based upon deterministic routing mechanism because it gives better latency at low packet injection and requires less resources while guaranteeing an orderly packet arrival. However, the disadvantage of deterministic routing is that it cannot respond to dynamic network condition such as congestion. When the network becomes congested, adaptive routing provides better throughput and lower latency by allowing alternate paths. In this paper, using simulation, we evaluate the performance of adaptive routing algorithm to deterministic routing strategy respected to throughput, power consumption and latency. The simulation environment is 2D-Mesh based NoC topology including different kinds of mapping Video Object Plane Decoder (VOPD) application onto this architecture. The experiment results prove the adaptive routing performance under network congestion occurrence.

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Section: Power Analysis V Simulation Results and Discussionmentioning

confidence: 99%

Section: Power Analysis V Simulation Results and Discussionmentioning

confidence: 99%

Assessing Routing Behavior on On-Chip-Network

Nguyen¹,

Ngo²,

Choi³

2006

2006 International Conference on Computer Engineering and Systems

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“…8 is the block diagram of VOPD. We use the optimized mapping [12] to simulate the application and a 6×5 mesh topology is implemented for VOPD. The central 4×3 is the twelve replaced IP of VOPD.…”

Section: B Performancementioning

confidence: 99%

A priority based output arbiter for NoC router

Chan

Tsai

Lai

et al. 2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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Network-on-Chip (NoC) is an on-chip communication method with good scalability and reliability. One of the most important issues of NoC design is low transmission latency design. In this paper, we propose a priority based output arbitration method to eliminate the congestion state of the NoC. By detecting and dispatching the packet requirements from different directions, the packets have different priorities. According to the priorities, the packets can pass the congested router in order. Simulation results demonstrate that the proposed method can reduce the transmission latency about 20% in uniformly distributed traffic and about 30% in hot-spot traffic when compare with the conventional router. In the router design, the new arbiter area overhead is less than 1%.

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“…An on-chip network must support guarantee for the delivery of multimedia data (real-time traffic) as well as the normal message-oriented communication (best-effort traffic). For example, in Nguyen, Ngo, and Choi (2005), a Video Object Plane Decoder (VOPD-16 cores), used in high-end video applications, has been designed and evaluated based on a 4 × 4 mesh topology similar to the one presented Figure1.…”

Section: Previous Workmentioning

confidence: 99%

Deadlock Free Routing Algorithm for Minimizing Data Packet Transmission in Network on Chip

Somasundaram

Plosila

2012

International Journal of Embedded and Real-Time Communication Systems

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Network on chip (NoC) has been proposed as a solution for addressing the design challenges of future high performance nanoscale architectures. In NoCs, the traditional routing schemes are routing packets through a single path or multiple paths from one source node to a destination node, minimizing the congestion in the routing architecture. Although these routing algorithms are moderately efficient, they are time dependent. To reduce overall data packet transmission time in the network, the authors consider a network with multiple sources and multiple destinations. Multi-dimensional routing problems appear naturally in several resource allocation problems, communication networks and wireless sensor networks. In this paper, the authors have constructed a deadlock-free multi-dimensional path routing algorithm for minimizing the congestion in NoC.

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Realization of Video Object Plane Decoder on On-Chip Network Architecture

Cited by 6 publications

References 8 publications

Assessing Routing Behavior on On-Chip-Network

Assessing Routing Behavior on On-Chip-Network

A priority based output arbiter for NoC router

Deadlock Free Routing Algorithm for Minimizing Data Packet Transmission in Network on Chip

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