A priority based output arbiter for NoC router

Chan, Cheng-Hao; Tsai, Kun-Lin; Lai, Feipei; Tsai, Shun-Hung

doi:10.1109/iscas.2011.5937966

Cited by 11 publications

(6 citation statements)

References 10 publications

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“…Router architectures have dominated the early NoC researches [9] and the first NoC design proposed the use of simplistic routers with deterministic routing algorithms in terms of RTL design. Since, the router [10] is a component that is to be used in every future versions of the system, its architecture options may be either revised or coexist in the same architecture (heterogeneous NoCs [11]), it should be designed as a reusable IP block [12].…”

Section: Router Designmentioning

confidence: 99%

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Design of Priority Based Reconfigurable Router in Network on Chip

2020

Informacije MIDEM

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Network on Chip (NoC) is an advanced integration design for communication networks while providing a solution to the traditional bus based System on Chip designs (SoC) too. A router is a key component which is considered as the backbone of communication in NoC. The objective of this work is to design a priority based reconfigurable router for NoC. Initially, a 4x4 Baseline router is designed and synthesised and then the channels inside the router are modified to achieve reconfiguration to improve the router's efficiency. In 4x4 Reconfigurable Router the slots are well utilized but prioritization portion is not considered. Routers are associated with switches to take data transfer decisions resulting in high power consumption. In order to overcome this problem, a new priority based reconfigurable router is designed. The design for this router is carried out using Verilog HDL and synthesized and simulated using Xilinx ISE Design Suite 14.3 and ModelSim-Altera 6.5b Software respectively. The corresponding results in terms of power, energy efficiency, area and delay are analysed and the proposed work gives better results than the conventional Baseline Router. Dizajn prioritetno nastavljivega usmerjevalnika v omrežju na čipuIzvleček: Omrežkje na čipu (NoC) je napredna integracija komunikacijskih omrežij z uporabo tradicionalnih sitemov na čipu na osnovi vodil (SoC). Usmerjevalnik predstavlja ključno komponento v komunikaciji preko NoC. Namen dela je razvoj prioritetno nastavljivega usmerjevalnika za NoC. V osnovi je uporabljen 4x4 usmerjevalnik, v kateremu so, za doseganje učinkovitosti, kanali naknadno razširjeni.Reže v nastavljivem usmerjevalniku so dobro uporabljene, vendar ne upoštevajo prioritet. Usmerjevalniki so povezani s stikali za prenos podatkov, ki imajo visoko porabo. Nastavljivi usmrjevalniku rešujejo problem visoke porabe. Dizajn usmerjevalnika je realiziran v Verilog HDL okolju in simuliran z Xilinx ISE Design Suite 14.3 in ModelSim-Altera 5.5b programsko opremo. Rezultati izkazujejo boljšo učinkovitost, nižjo porabo in zakasnitev predlaganega usmerjevalnika.

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Section: Router Designmentioning

confidence: 99%

“…It provides the selection process of selecting the operation to be carried out by the router. The FSM controller here is used to display the work to be done by the router [12]. In general, a synchronous circuit is a digital circuit in which the changes in the state of memory elements are synchronized by a clock signal.…”

Section: Arbiter Unitmentioning

confidence: 99%

Design of Priority Based Reconfigurable Router in Network on Chip

2020

Informacije MIDEM

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“…Router [4] Router [8] Router [12] Router [1] Router [5] Router [9] Router [13] Router [2] Router [6] Router [10] Router [14] Router [3] Router [7] Router [11] Router [15] Core[0]…”

Section: Router[0]mentioning

confidence: 99%

“…The trend of increasing the processing elements on chip raises communication complexity and affects the scalability of on chip systems. The parasitic effects becomes dominant with large number of interconnects [2]. Cost of SoC system is highly influenced by interconnects which pays important role in power consumption, performance and overall size of the system.…”

Section: Introductionmentioning

confidence: 99%

Performance Evaluation of Modern Network-on-Chip Router Architectures

Latif¹

2016

IJCDS

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On chip interconnection networks simplify the challenges of integrating large number of processing elements. Routers are backbone of networks. Buffers and crossbar in router consumes significant area and power of network. They have huge impact on overall performance and cost of network. Dual Xbar router architecture combines buffered and bufferless feature to reduce buffer read/write energy with dual crossbars. While Switch folding technique introduced to reduce wire density and decrease muxes in crossbar by increasing resource utilization. In this paper, we propose Folded Dual Xbar architecture by combining the Dual Xbar and Folding technique in order to get advantages of both architectures. Performance of architectures is implemented and evaluated using OMNET++ platform by applying multiple traffic patterns under different load conditions. We further calculated buffered and bufferless events to estimate the reduction in buffer read/write energy. Simulation results shows that there is slight increase in throughput and reduction in buffer read/write energy by average 46% at high loads in proposed 2-Folded Dual Xbar as compared to conventional architecture. Proposed 3-Folded Dual Xbar results at least 16.6 % increase in throughput as compared to conventional architecture with 43-45% reduced buffer read/write energy but slight increase in crossbar. Throughput of 3-Folded Dual Xbar decreased only by 5-7% as compared to Dual Xbar with distributed wire density advantage..

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“…Park et al proposes a method for equality of service, which achieves the global fairness by providing the service to each node with fewer resource requirements [8]. A priority based output arbitration method to reduce the congestion of the NoC is proposed in [9]. Two new arbitration mechanisms to obtain fair link bandwidth are introduced in [10], which can achieve almost absolute fairness of link bandwidth.…”

Section: Introductionmentioning

confidence: 99%

BARR: Congestion aware scheduling algorithm for Network-on-Chip router

Wang

et al. 2017

IEICE Electron. Express

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Scheduling algorithm is crucial to the performance of the Network-on-chip router. Different from traditional scheduling algorithms that concentrate on local fairness, we propose a congestion-aware scheduling algorithm based on input buffer of downstream router. The scheduling algorithm keeps a match dynamically between input and output by detecting the flits number to be transferred in the same packet. It can reduce network congestion especially under heavy traffic loads. Compared to RRM and iSLIP algorithm, the new scheduling algorithm can increase the saturation throughput by 8.2% and reduce the average communication latency by 7.8% under non-uniform traffic.

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A priority based output arbiter for NoC router

Cited by 11 publications

References 10 publications

Design of Priority Based Reconfigurable Router in Network on Chip

Design of Priority Based Reconfigurable Router in Network on Chip

Performance Evaluation of Modern Network-on-Chip Router Architectures

BARR: Congestion aware scheduling algorithm for Network-on-Chip router

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