Two high holding voltage silicon controlled rectifiers (SCRs) with segmented layout for high-robust ESD protection are proposed, which are called SeSCR (segmented SCR) and anti-SeSCR (anti-segmented SCR), implemented in a 0.6 μm silicon on insulator (SOI) process. The transmission line pulse (TLP) characterisation results show that the holding voltage of the proposed structures can be elevated and adjusted with new layout topologies and different width of the segmentations for specific purposes. Meanwhile, the equivalent schematics and mechanisms of the segmented SCRs are also discussed.
This paper presents a novel scheme for IF digital software radio receiver application, which integrates a high performance AID converter and high-speed digital down converter (DDC) block into a SoC (system on chip) based on 32-bit RISC CPU. The proposed design can transform intermediate frequenc y (IF) analog signal to baseband digital signal and realize the real-time baseband signal processing. The simulation results indicate that The SFDR of ADC can achieve 88dB, and the SFDR of the DDC can reach to 70.59dBFS. The s y nthesized results of digital parts for the proposed SoC architecture on 0.18um CMOS technolog y reveals a maximum clock frequenc y of 116MHz and a total area of digital parts is 5.662mm 2 , and the corresponding power consumption is below 150 mW • The ADC can reach to 250MSPS, whose power consumption is 263.6mW. The test results illuminates that the chip can work well. This design will have a good potential for wireless communication applications.
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