2017
DOI: 10.1049/el.2017.2390
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High holding voltage SCRs with segmented layout for high‐robust ESD protection

Abstract: Two high holding voltage silicon controlled rectifiers (SCRs) with segmented layout for high-robust ESD protection are proposed, which are called SeSCR (segmented SCR) and anti-SeSCR (anti-segmented SCR), implemented in a 0.6 μm silicon on insulator (SOI) process. The transmission line pulse (TLP) characterisation results show that the holding voltage of the proposed structures can be elevated and adjusted with new layout topologies and different width of the segmentations for specific purposes. Meanwhile, the… Show more

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Cited by 12 publications
(8 citation statements)
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“…However, the holding voltage of SCR devices are insensitive to the variation of lateral dimension. [4,10] Therefore, the lateral dimension increase of 2 µm is not the main reason for the increase in the holding voltage of EGDTSCR. In the proposed EGDTSCR, the ESD current discharge capacity of the surface gated diode is stronger than that of the parasitic PNP + in MLSCR, which is the main reason for that the EGDTSCR can achieve a higher holding voltage than the MLSCR.…”
Section: Tlp Measurements and Discussionmentioning
confidence: 99%
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“…However, the holding voltage of SCR devices are insensitive to the variation of lateral dimension. [4,10] Therefore, the lateral dimension increase of 2 µm is not the main reason for the increase in the holding voltage of EGDTSCR. In the proposed EGDTSCR, the ESD current discharge capacity of the surface gated diode is stronger than that of the parasitic PNP + in MLSCR, which is the main reason for that the EGDTSCR can achieve a higher holding voltage than the MLSCR.…”
Section: Tlp Measurements and Discussionmentioning
confidence: 99%
“…Under the constraints of chip area, segmentation techniques are introduced to reduce emitter injection efficiency of SCR device and achieve relatively high holding voltages. [8][9][10] However, the segmentation topology may cause current crowding, resulting in a deterioration in the ESD robustness. [11] Moreover, none of the above methods can simultaneously increase the holding voltage while maintaining a high failure current (I t2 ).…”
Section: Introductionmentioning
confidence: 99%
“…Of course, static electricity may cause damage to the chip in any link, and this damage is generally fatal 8 . When charged objects touch the pins of the chip, or the pins of the chip with internal charges touch the external conductors, electrostatic charges will flow in or out from the pins of the chip, and these discharging processes may damage the internal circuits of the chip, reduce their performance or make them unusable 9 . Although electronic components are developing in the direction of intelligence, miniaturization and reliability, ESD phenomenon is still the primary problem to be solved in integrated circuits.…”
Section: Introductionmentioning
confidence: 99%
“…The ESD protection diodes are considered to be promising in advanced technology as an ESD protection device [ 6 , 7 , 8 ]. The diode-string silicon-controlled rectifier (DSSCR) with high robustness is also considered as the ESD protection device for previous technology nodes [ 10 , 11 , 12 , 13 , 14 , 15 ], but it is no longer suitable for the 7 nm technology due to its high leakage and large snapback for latch-up. ESD design for the FinFET process is still a great challenge.…”
Section: Introductionmentioning
confidence: 99%