Enhanced gated-diode-triggered silicon-controlled rectifier for robust electrostatic discharge (ESD) protection applications*

Song, Wenqiang; Hou, Fei; Du, Feibo; Liu, Zhiwei; Liou, Juin J.

doi:10.1088/1674-1056/ab9de6

Cited by 4 publications

(3 citation statements)

References 18 publications

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“…Silicon controlled rectifier (SCR) is popularly used due to its efficient release capacity per unit area, but the working mechanism of SCR under negative pulse is of diode. [1][2][3] In the control bus, the signal from the A/B port is bidirectional, the ESD protection should be considered to be also bidirectional, the DDSCR is selected, and the DDSCR device can optimize the ESD characteristics of the DDSCR by changing the structure and size. The deep snapback phenomenon of DDSCR will also cause some problems with high trigger voltage and low holding voltage.…”

Section: Introductionmentioning

confidence: 99%

New DDSCR structure with high holding voltage for robust ESD applications*

Zhou¹,

Jin²,

Wang³

et al. 2021

Chinese Phys. B

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A novel dual direction silicon-controlled rectifier (DDSCR) with an additional P-type doping and gate (APGDDSCR) is proposed and demonstrated. Compared with the conventional low-voltage trigger DDSCR (LVTDDSCR) that has positive and negative holding voltages of 13.371 V and 14.038 V, respectively, the new DDSCR has high positive and negative holding voltages of 18.781 V and 18.912 V in a single finger device, respectively, and it exhibits suitable enough positive and negative holding voltages of 14.60 V and 14.319 V in a four-finger device for ±12-V application. The failure current of APGDDSCR is almost the same as that of LVT-DDSCR in the single finger device, and the four-finger APGDDSCR can achieve positive and negative human-body model (HBM) protection capabilities of 22.281 kV and 23.45 kV, respectively, under 40-V voltage of core circuit failure, benefitting from the additional structure. The new structure can generate a snapback voltage on gate A to increase the current gain of the parasitic PNP in holding voltage. Thus, a sufficiently high holding voltage increased by the structure can ensure that a multi-finger device can also reach a sufficient holding voltage, it is equivalent to solving the non-uniform triggering problem of multi-finger device. The operating mechanism and the gate voltage are both discussed and verified in two-dimensional (2D) simulation and experiemnt.

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Section: Introductionmentioning

confidence: 99%

New DDSCR structure with high holding voltage for robust ESD applications*

Zhou¹,

Jin²,

Wang³

et al. 2021

Chinese Phys. B

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show abstract

“…Novel ESD protecting devices are frequently designed to mitigate such concerns. [1][2][3][4] Meanwhile, high temperature is a typical environment for integrated circuits. [5,6] The assembly and operation of integrated circuits in some cases take place at elevated temperatures.…”

Section: Introductionmentioning

confidence: 99%

Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures*

Wang¹,

Li²,

Zhao³

et al. 2021

Chinese Phys. B

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Trigger characteristics of electrostatic discharge (ESD) protecting devices operating under various ambient temperatures ranging from 30 °C to 195 °C are investigated. The studied ESD protecting devices are the H-gate NMOS transistors fabricated witha 0.18-μm partially depleted silicon-on-insulator (PDSOI) technology. The measurements are conducted by using a transmission line pulse (TLP) test system. The different temperature-dependent trigger characteristics of grounded-gate (GGNMOS) mode and the gate-triggered (GTNMOS) mode are analyzed in detail. The underlying physical mechanisms related to the effect of temperature on the first breakdown voltage V T1 are investigated through the assist of technology computer-aided design (TCAD) simulation.

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“…In recent research, gate structures are widely used to improve the ESD performance of SCR structures [28][29][30]. It gives us inspiration that we can use the gate structure to create a novel discharging mechanism to increase the holding voltage of the traditional SCR structure.…”

Section: Introductionmentioning

confidence: 99%

Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

Zhong

Wang

Jin

et al. 2021

IEICE Electron. Express

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The current aggregation mechanism created by the gate structure is proposed for electrostatic discharging (ESD). Through device simulation, the size-expanded gate structure in gate-control dual-direction silicon controlled rectifier (GC-DDSCR) is found to aggregate the surface parasitic current path and the main SCR current path. The SCR current path is consequently twisted and extended to increase the holding voltage (Vh). Two GC-DDSCRs are fabricated in a 0.5μm CMOS technology and tested by transmission line pulse (TLP). The Vh increases from 13.84V to 16.44V as the gate size expands from 2.5μm to 4.5μm. The mechanism of current aggregation is verified.

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Enhanced gated-diode-triggered silicon-controlled rectifier for robust electrostatic discharge (ESD) protection applications*

Cited by 4 publications

References 18 publications

New DDSCR structure with high holding voltage for robust ESD applications*

New DDSCR structure with high holding voltage for robust ESD applications*

Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures*

Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

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