Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures*

Wang, Jiaxin; Li, Xiaojing; Zhao, Fukun; Zeng, Chong; Li, Duoli; Gao, Linchun; Li, Jiang-Jiang; Li, Bo; Han, Zhengsheng; Luo, Jiajun

doi:10.1088/1674-1056/abe2fe

Cited by 3 publications

(3 citation statements)

References 17 publications

(19 reference statements)

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“…口, 即触发电压小于栅氧击穿电压以避免损坏内部电路, 维持电压大于电源工作电压以避免闩锁 [6−8] . 集成电路的封装和部分操作在某些情况下是在高温环境中进行的 [9] , 由于ESD参数的热致变化 [10] , Li等 [11] 研究了二极管、二极管串及栅接地N沟道金属-氧化物-半导体(grounded-gate N-channel metal oxide semiconductor, GGNMOS) 在-40-110 ℃ 的温度范围内ESD特性的温度依赖性. Wang等 [12] 介绍了GGNMOS和栅触发NMOS (GTNMOS)的触发电压随温度的变化特性, 并对其内部物理机制作了详细研究.…”

Section: 一般来说 Esd防护结构设计应遵循esd设计窗unclassified

Effect of high-temperature on holding characteristics in MOSFET ESD protecting device

Li¹,

Cai²,

Zeng³

et al. 2022

Acta Phys. Sin.

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The holding voltage of electrostatic discharge (ESD) protective structure is the critical parameter to determine the latch-up performance of the protecting device, but the thermal change of ESD device parameters exposes the protecting device to latch-up risk in high ambient temperature. In this paper, the holding characteristics of the ESD protection device under various ambient temperatures ranging from 30 to 195℃℃ are studied. The investigated ESD structure is the NMOS transistors fabricated with the 0.18 μm partially depleted silicon-on-insulator (PDSOI) process. The ESD characteristics of the device are measured by the transmission line pulse (TLP) test system at different ambient temperatures. The test results show that the holding voltage (VH) decreases with the increasing temperature. TCAD simulation is carried out to support and analyze the experiment results, and the same trend of VH versus temperature is obtained. Through the analysis of simulation results and theoretical derivation, the underlying physical mechanisms related to the effects of temperature on VH and holding current (IH) are discussed in detail. When the Drain is subject to the same current pulsing, Source and Body is grounded, the distributions of current density, electric potential, and injected electron density of NMOS under various temperatures are extracted and analyzed. When the Drain, Source, and Body are grounded, the distributions of the electrostatic field under various temperatures are extracted and analyzed. The distributions of electric potential in NMOS indicate that voltage drop on the Drain-Body junction (VDB) is affected by ambient temperature significantly, and the variation of VDB dominates the variation trend of VH with increasing temperature. The decreasing electrostatic field and increasing injected electron density with decreasing temperature contribute to the decreasing VDB. The trend of IH and parasitic Body resistance (RBody) weakens the temperature dependence of the VH. The current gain of parasitic bipolar transistor (β) decreases with growing ambient temperature, which is the main contributor to the decreasing IH. Therefore, increasing IH and RBody is helpful to reduce the temperature dependence of the latch-immune ESD protection structure.

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Section: 一般来说 Esd防护结构设计应遵循esd设计窗unclassified

Effect of high-temperature on holding characteristics in MOSFET ESD protecting device

Li¹,

Cai²,

Zeng³

et al. 2022

Acta Phys. Sin.

Self Cite

View full text Add to dashboard Cite

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“…These ESD protection requirements are necessary for industry-level chips to withstand any potential electrostatic disturbances. Currently, commonly used on-chip ESD protection devices include diodes [3], gate-grounded NMOS (GGNMOS) [4,5], and silicon-controlled rectifiers (SCRs) [6,7]. Diodes have a simple structure and fast response speed, typically used for low-voltage I/O protection, but they are not suitable for circuits with operating voltages above 3.3 V. Increasing the number of diodes in series leads to higher conduction resistance and leakage current.…”

Section: Introductionmentioning

confidence: 99%

Dual-directional SCR device with dual-gate controlled mechanism for ESD protection in photoelectric chip

Liu,

Wang,

Yang

et al. 2024

Semicond. Sci. Technol.

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The dual-directional silicon-controlled rectifier (DDSCR) is an electrostatic discharge (ESD) protection device. It can provide positive and negative ESD surge paths and has excellent robustness. However, industry-level sensors operating in strong electromagnetic interference environments impose higher reliability requirements on photoelectric chips. This paper proposed a novel DDSCR with a dual-gate controlled mechanism. By incorporating the gate diode triggering and the gate field modulation mechanism into the traditional DDSCR, and further utilizing additional parasitic PNP transistors for diversion, the proposed device exhibits significantly improved ESD characteristics. Measurement results indicate that, compared to DDSCR, the proposed device exhibits a 27.5% reduction in trigger voltage (Vt1), a 96.1% improvement in holding voltage (Vh), and achieves an equivalent Human Body Model (HBM) protection level of 11.45 kV, demonstrating exceptional design area efficiency. The experimental findings validate the effectiveness of the proposed device in 5 V photoelectric chip applications.

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“…7 Liang et al 8 investigated the impact of temperature on the ESD protection characteristics of various thyristors and diodes within the range of 300-500 K, they found that the holding voltage of all types of devices decreased as the temperature increased, while the relationship between the breakdown voltage and temperature varied depending on the trigger conditions of each device. Wang et al 9 presented the variation characteristics of the holding voltage of 0.18 μm H-NMOS within the temperature range of 30-195 • C, and conducted a detailed analysis. Tazzoli et al 10 proposed a high holding voltage SCR structure and investigated the temperature dependence of the device.…”

Section: Introductionmentioning

confidence: 99%

Temperature dependence of ESD effects on 28 nm FD‐SOI MOSFETs

Xiao

Liu

Zhang

et al. 2023

Engineering Reports

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The failure mechanisms caused by electrostatic discharge (ESD) effects at ambient temperatures ranging from −75 to 125°C are investigated by Silvaco TCAD simulator. The devices are NMOS transistors fabricated with 28 nm fully depleted silicon‐on‐insulator (FDSOI) technology. Results indicate that with an increase in temperature, the first breakdown voltage of the device decreased by 27.32%, while the holding voltage decreased by approximately 8.49%. The total current density, lattice temperature, potential, and so forth were extracted for a detailed insight into the failure process. These findings provide valuable references for the design and development of ESD protection devices applied at different temperature ranges.

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Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures*

Cited by 3 publications

References 17 publications

Effect of high-temperature on holding characteristics in MOSFET ESD protecting device

Effect of high-temperature on holding characteristics in MOSFET ESD protecting device

Dual-directional SCR device with dual-gate controlled mechanism for ESD protection in photoelectric chip

Temperature dependence of ESD effects on 28 nm FD‐SOI MOSFETs

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