Temperature dependence of ESD effects on 28 nm FD‐SOI MOSFETs

Abstract

The failure mechanisms caused by electrostatic discharge (ESD) effects at ambient temperatures ranging from −75 to 125°C are investigated by Silvaco TCAD simulator. The devices are NMOS transistors fabricated with 28 nm fully depleted silicon‐on‐insulator (FDSOI) technology. Results indicate that with an increase in temperature, the first breakdown voltage of the device decreased by 27.32%, while the holding voltage decreased by approximately 8.49%. The total current density, lattice temperature, potential, and so forth were extracted for a detailed insight into the failure process. These findings provide valuable references for the design and development of ESD protection devices applied at different temperature ranges.