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Electrostatic discharge (ESD) is an event that sends current through an integrated circuit (IC). This paper reviews the impact of ESD on the IC industry and details the four stages of an ESD event: 1) charge generation, 2) charge transfer, 3) device response, and 4) device failure. Topics reviewed are charge generation mechanisms, models for ESD charge transfer, electrical conduction mechanisms, and device damage mechanisms leading to circuit failure.

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This paper presents a study of the Fuzzy ARTMAP neural network in designing cascaded gratings and Frequency Selective Surfaces (FSS) in general. Conventionally, trial and error procedures are used until an FSS matches the design criteria. One way of avoiding this laborious and manual process is to use neural networks. A neural network can be trained to predict the dimensions of the metallic patches(or apertures), their distance of separation, their shape, and the number of layers required in a multilayer structure which gives the desired frequency response. In the past, to achieve this goal, the back propagation (back-prop) learning algorithm was used in conjunction with an inversion algorithm. Unfortunalety, the back-prop algorithm sometimes has problems with convergence. In this work the Fuzzy ARTMAP neural network is utilized. The Fuzzy ARTMAP is faster to train than the back-prop and it does not require an inversion algorithm to solve the FSS problem. Most importantly, its convergence is guaranteed. Several results (frequency responses) from cascaded gratings for various angles of wave incidence, layer separation, width strips, and interstrip separation are presented and discussed. O819415472/941'$6 SPIE Vol. 2243 / 571 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/22/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

Low-power, high-speed dynamic comparators are highly desirable in the design of highspeed analog-to-digital converters (ADC) and digital I/O circuits. Most dynamic comparators use a pair of cross-coupled inverters as the latching stage, which provides strong positive feedback, to accelerate the comparison and reduce the static power consumption. The delay of the comparator is mainly determined by the total effective transconductance of the latching stage. The delay not only limits the maximum operating frequency but also extends the period of the metastable state of the latching stage; hence, it increases energy consumption. However, at the beginning of the comparison phase, the conventional latching stage has two transistors with zero gate-to-source voltage, which degrade the total effective transconductance of the latching stage. In this paper, a novel low-power, high-speed dynamic comparator with a new latching stage is presented. The proposed latching stage uses separated gate-biasing cross-coupled transistors instead of the conventional cross-coupled inverter structure. The simple proposed latching stage improves its effective total transconductance at the beginning of the comparison phase, which leads to a much faster comparison and lowers energy consumption. The comparator is analyzed and compared to its prior type in terms of delay and power consumption via simulations and measurements. The experimental results demonstrate that the proposed comparator operates from a 1.2-V supply and consumes 110-fJ energy per comparison, with sampling speeds up to 2 GS/s.

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