Design and implementation of a mixed SoC for IF digital software radio receiver

Abstract

This paper presents a novel scheme for IF digital software radio receiver application, which integrates a high performance AID converter and high-speed digital down converter (DDC) block into a SoC (system on chip) based on 32-bit RISC CPU. The proposed design can transform intermediate frequenc y (IF) analog signal to baseband digital signal and realize the real-time baseband signal processing. The simulation results indicate that The SFDR of ADC can achieve 88dB, and the SFDR of the DDC can reach to 70.59dBFS. The s y nthesized results of digital parts for the proposed SoC architecture on 0.18um CMOS technolog y reveals a maximum clock frequenc y of 116MHz and a total area of digital parts is 5.662mm 2 , and the corresponding power consumption is below 150 mW • The ADC can reach to 250MSPS, whose power consumption is 263.6mW. The test results illuminates that the chip can work well. This design will have a good potential for wireless communication applications.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

“…The architecture of the proposed mixed-signal reconfigurable SoC is depicted in Fig. 1, wherein a 32-bit reduced instruction-set compute (RISC) CPU is taken as the microprocessor [8] , the multi-layer bus architecture based on advanced microcontroller bus architecture (AMBA) system is adopted and all peripheral IPs connect to the bus through a standard bus interface. The serial flash controller (SflashCTRL) connects to the outside serial flash chip that stores the system program.…”

“…5, which consists of 9-stage pipeline, digital calibration, control logic, internal reference generator, clock circuits and output driver. The 9-stage pipeline includes multi-stage pipeline body and each stage includes multi-bits, which are disassociated by 4 bit + 3 bit + 6 × 1.5 bit + 3 bit respectively, wherein the first-stage circuit is realized with the analog front-end without sample and hold, the first stage includes 4 bits, the second stage includes 3 bits, then 6 stages (3rd-8th stages) of 1.5 bit/stage follow and at last the 9th stage of 3 bits acts as the end of the architecture, all those bits act together as a 14-bit redundancy pipeline ADC [8,[15][16][17] .…”

“…To this point, there is an important advantage that the mixed RSoC could provide significant system cost savings, which would result mainly from shorter exploitation cycles and lower system integration risk. Without these, many systems would be forced to afford the discrete component implementations, which would bring the accompanying increase of system size, cost, integration risk, and power consumption [8] .…”

Design of a SoC for Intermediate Frequency Digital Receiver

“…After the CPU issues instructions, data can be read out from the RAM1 through the dual port RAM controller, when the system needs that. To facilitate the signal processing system, the system integrates a 32KB data memory RAM2, as well as UART, GPIO, SPI and TIMERS and other peripherals [5] .…”

“…The DDC is divided into I and Q channels, the two data channels share the same NCO unit. The digital filter group was divided into the CIC (cascaded integrator comb) filter module, CIC compensation filter modules and the half-band filter module [5] . DDC block diagram is shown in Fig.4.…”