Focusing on meeting the requirements for embedded applications of faster switching and sensing, lower-power consumption, higher reliability, longer cycling endurance, and higher temperature retention, a lot of progress in the phase change memory (PCM) field has been made, including materials improvement, process optimization, new circuits design, and better operation algorithms. Finally, a 128 MB embedded PCM chip has been demonstrated in 40 nm node. Using carbon-doped Ge 2 Sb 2 Te 5 phase change material and 3 nm thick heating bottom electrode contact (BEC) with nitride coating, a resistance ratio of more than two orders of magnitude has been achieved in Reset and Set states. Combined with the parasitic matched sensing circuit, optimized ramp-down SET pulses, adaptive pre-read and write-verify methods, and automatic configure and test procedures, the chip exhibits excellent data retention and endurance characteristics with minimum program time of 200 ns, and the Reset/Set resistance ratio becomes even larger after 260 C soldering test. The estimated data retention time is 10 years at 128 C, and in a 128 MB full integrated chip the endurance over 10 9 cycles is achieved. It is confirmed that this PCM technology is suitable for embedded applications, especially for those with crucial requirements of high access speed, high thermal stability, and cycling endurance.

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A 64 Mbit phase change memory chip is fabricated in 40 nm CMOS technology. An improved fully-differential sense amplifier with a bias voltage instead of the reference resistor branch is proposed to diminish the chip area. The transient response capability of the proposed sense amplifier is improved by removing the large parasitic capacitance of bit line in the feedback network. Smaller parasitic capacitance is also obtained by the separated programming and reading transmission gates to speed up the read operation. The hierarchical bit line architecture is used to reduce the length of bit line, and thus favorable read performance can be achieved.

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Multi-level cell (MLC) phase change memory (PCM) can not only effectively multiply the memory capacity while maintaining the cell area, but also has infinite potential in the application of the artificial neural network. The write and verify scheme is usually adopted to reduce the impact of device-to-device variability at the expense of a greater operation time and more power consumption. This paper proposes a novel write operation for multi-level cell phase change memory: Programmable ramp-down current pulses are utilized to program the RESET initialized memory cells to the expected resistance levels. In addition, a fully differential read circuit with an optional reference current source is employed to complete the readout operation. Eventually, a 2-bit/cell phase change memory chip is presented with a more efficient write operation of a single current pulse and a read access time of 65 ns. Some experiments are implemented to demonstrate the resistance distribution and the drift.

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As information technology is moving toward the era of big data, the traditional Von-Neumann architecture shows limitations in performance. The field of computing has already struggled with the latency and bandwidth required to access memory (“the memory wall”) and energy dissipation (“the power wall”). These challenging issues, such as “the memory bottleneck,” call for significant research investments to develop a new architecture for the next generation of computing systems. Brain-inspired computing is a new computing architecture providing a method of high energy efficiency and high real-time performance for artificial intelligence computing. Brain-inspired neural network system is based on neuron and synapse. The memristive device has been proposed as an artificial synapse for creating neuromorphic computer applications. In this study, post-silicon nano-electronic device and its application in brain-inspired chips are surveyed. First, we introduce the development of neural networks and review the current typical brain-inspired chips, including brain-inspired chips dominated by analog circuit and brain-inspired chips of the full-digital circuit, leading to the design of brain-inspired chips based on post-silicon nano-electronic device. Then, through the analysis of N kinds of post-silicon nano-electronic devices, the research progress of constructing brain-inspired chips using post-silicon nano-electronic device is expounded. Lastly, the future of building brain-inspired chips based on post-silicon nano-electronic device has been prospected.