Methods to speed up read operation in a 64 Mbit phase change memory chip

Abstract

A 64 Mbit phase change memory chip is fabricated in 40 nm CMOS technology. An improved fully-differential sense amplifier with a bias voltage instead of the reference resistor branch is proposed to diminish the chip area. The transient response capability of the proposed sense amplifier is improved by removing the large parasitic capacitance of bit line in the feedback network. Smaller parasitic capacitance is also obtained by the separated programming and reading transmission gates to speed up the read operation. The hierarchical bit line architecture is used to reduce the length of bit line, and thus favorable read performance can be achieved.

Enhanced read performance for phase change memory using a reference column

“…V bg is the bandgap voltage. The proposed method uses one voltage (V clamp ) to generate I refnew and I read , which is different from previous methods which use two different voltages/circuits to generate I read and I ref [6,7,8]. In the proposed method, I refnew and I read are more likely to have a similar variation trend.…”

“…In the reference side, there are one selected cell, n À 1 unselected cells, one selected RTG and m À 1 unselected RTGs; in the array, there are also one selected cell, n À 1 unselected cells, one selected RTG and m À 1 unselected RTGs. Different from the conventional methods which use a constant reference current [6,7], the reference cell and the selected cell have the same parasitic elements in the proposed method. Fig.…”

“…In this work, the GST resistance is modeled base on the conventional GST element used in a 40 nm PCM device [6]. The set resistance distribution is from a few KΩ to 100 KΩ and the reset resistance distribution is from 1 MΩ to dozens of MΩ.…”

“…Accomplished in process & mismatch analysis, three times standard deviation (3) is used as the variances of parameters and mismatch of MOS and resistor. The GST device is modeled as the resistance distribution in order to reflect the effect of process variation [6]. In each simulation, 4000 trials were run.…”

Enhancing the Performance of Phase Change Memory for Embedded Applications

“…A constant reference is widely used in the conventional sensing circuits for planar NVMs . Considering the intuitionistic characteristic of data stored in PCM is resistance, read operation is always achieved by applying a clamp voltage to BL of the addressed cell and measuring the amount of current passing through the target memory cell.…”