Enhanced read performance for phase change memory using a reference column

Abstract

A reference column is employed to improve the read performance of phase change memory (PCM). In this way, a changeable reference current replaces the constant one; both the reference cell and the selected cell have the same bit line (BL) parasitic parameters and read transmission gate parasitic parameters in the read operation. Simulated in a 40 nm CMOS process, read access time of 4-Mb PCM is 30.65 ns with 190.9 ns improvement. Monte Carlo simulations show a 80.5 ns worst read access time compared to the conventional 1.58 µs.

Near-threshold SIDO DC-DC converter with a high-precision ZCD for phase change memory chip

“…Flash memory can only work in block manipulation. Comparing with traditional nonvolatile memory, PCRAM can be changed resistance to store data by different current, so it can be operated bit-by-bit and reduce power consumption in wireless senor network [13,14]. In PCRAM chips, write operation needs high power voltage to ensure success, and read and logic operation use low power voltage to reduce power consumption.…”