A Single-Reference Parasitic-Matching Sensing Circuit for 3-D Cross Point PCM

Lei, Yu; Chen, Houpeng; Wang, Qian; Li, Xi; Li, Xiaoyun; Tian, Zhen; Zhang, Song

doi:10.1109/tcsii.2017.2729665

Cited by 8 publications

(3 citation statements)

References 13 publications

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“…The traditional readout circuit can not meet the requirements of high access embedded applications. We have concluded the main factors that affect the read operation and their relationships to the array for the first time . Besides a new read circuit is proposed to overcome the shortcoming of traditional circuits in 128 MB PCM.…”

Section: Architecture and Optimized Designsmentioning

confidence: 93%

Enhancing the Performance of Phase Change Memory for Embedded Applications

Chen

Xie

et al. 2019

Physica Rapid Research Ltrs

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Focusing on meeting the requirements for embedded applications of faster switching and sensing, lower-power consumption, higher reliability, longer cycling endurance, and higher temperature retention, a lot of progress in the phase change memory (PCM) field has been made, including materials improvement, process optimization, new circuits design, and better operation algorithms. Finally, a 128 MB embedded PCM chip has been demonstrated in 40 nm node. Using carbon-doped Ge 2 Sb 2 Te 5 phase change material and 3 nm thick heating bottom electrode contact (BEC) with nitride coating, a resistance ratio of more than two orders of magnitude has been achieved in Reset and Set states. Combined with the parasitic matched sensing circuit, optimized ramp-down SET pulses, adaptive pre-read and write-verify methods, and automatic configure and test procedures, the chip exhibits excellent data retention and endurance characteristics with minimum program time of 200 ns, and the Reset/Set resistance ratio becomes even larger after 260 C soldering test. The estimated data retention time is 10 years at 128 C, and in a 128 MB full integrated chip the endurance over 10 9 cycles is achieved. It is confirmed that this PCM technology is suitable for embedded applications, especially for those with crucial requirements of high access speed, high thermal stability, and cycling endurance.

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Section: Architecture and Optimized Designsmentioning

confidence: 93%

Enhancing the Performance of Phase Change Memory for Embedded Applications

Chen

Xie

et al. 2019

Physica Rapid Research Ltrs

Self Cite

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“…An Ovonic threshold switching (OTS) selector is one promising candidate for PCRAM owing to its large drive current. Researchers at SIMIT have successfully prepared an OTS device (14) and designed a 3D PCRAM circuit (15). In the future, SIMIT plans to develop one selector-one resistor (1S1R) single and integrated nanotechnology compatible with CMOS technology using a high-density crossbar structure, and further integrate them with advanced logic processes to achieve high-density storage chips.…”

Section: Terahertz (Thz) Solid-state Technologiesmentioning

confidence: 99%

A Fast-Transient-Response NMOS LDO with Wide Load-Capacitance Range for Cross-Point Memory

et al. 2022

Sensors

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In this paper, a fast-transient-response NMOS low-dropout regulator (LDO) with a wide load-capacitance range was presented to provide a V/2 read bias for cross-point memory. To utilize the large dropout voltage in the V/2 bias scheme, a fast loop consisting of NMOS and flipped voltage amplifier (FVA) topology was adopted with a fast transient response. This design is suitable to provide a V/2 read bias with 3.3 V input voltage and 1.65 V output voltage for different cross-point memories. The FVA-based LDO designed in the 110 nm CMOS process remained stable under a wide range of load capacitances from 0 to 10 nF and equivalent series resistance (ESR) conditions. At the capacitor-less condition, it exhibited a unity-gain bandwidth (UGB) of approximately 400 MHz at full load. For load current changes from 0 to 10 mA within an edge time of 10 ps, the simulated undershoot and settling time were only 144 mV and 50 ns, respectively. The regulator consumed 70 µA quiescent current and achieved a remarkable figure-of-merit (FOM) of 1.01 mV. At the ESR condition of a 1 µF off-chip capacitor, the simulated quiescent current, on-chip capacitor consumption, and current efficiency at full load were 8.5 µA, 2 pF, and 99.992%, respectively. The undershoot voltage was 20 mV with 800 ns settling time for a load step from 0 to 100 mA within the 10 ps edge time.

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A Single-Reference Parasitic-Matching Sensing Circuit for 3-D Cross Point PCM

Cited by 8 publications

References 13 publications

Enhancing the Performance of Phase Change Memory for Embedded Applications

Enhancing the Performance of Phase Change Memory for Embedded Applications

Sponsored Collection | 90 Years of Scientific Advances at the Shanghai Institute of Microsystem and Information Technology, CAS

A Fast-Transient-Response NMOS LDO with Wide Load-Capacitance Range for Cross-Point Memory

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