We report that a Ni–InGaAs alloy can be used as a source/drain (S/D) metal for InGaAs metal–oxide–semiconductor field-effect transistors (MOSFETs), allowing us to employ the salicide-like self-align S/D formation. We also introduce Schottky barrier height (SBH) engineering process by increasing the indium content of InxGa1-xAs channels, which successfully reduces SBH down to zero. We propose a fabrication process for self-aligned metal S/D MOSFETs using Ni–InGaAs and demonstrate successful operation of the metal S/D InxGa1-xAs MOSFETs. The In0.7Ga0.3As MOSFETs exhibit an S/D resistance (RSD) that is 1/5 lower than that in P–N junction devices and a high peak mobility of 2000 cm2 V-1 s-1.

We have demonstrated thin body III-V-semiconductor-on-insulator (III-V-OI) n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) on a Si wafer fabricated using a novel direct wafer bonding (DWB) process. A 100-nm-thick InGaAs channel was successfully transferred by the low damage and low temperature DWB process using low energy electron cyclotron resonance (ECR) plasma. The transferred InGaAs-OI nMOSFET on the Si wafer exhibited a high electron channel mobility of 1200 cm 2 ÁV À1 Ás À1 , indicating that the present DWB process allows us to form thin III-V-OI channels without serious plasma and bonding damage. This technology is expected to open up the possibility of integrating the ultrathin body III-V-OI MOSFETs on Si platform.

A simple and feasible method for fabricating high-quality and highly reliable GaN-based metal-oxide-semiconductor (MOS) devices was developed. The direct chemical vapor deposition of SiO 2 films on GaN substrates forming Ga-oxide interlayers was carried out to fabricate SiO 2 / GaO x /GaN stacked structures. Although well-behaved hysteresis-free GaN-MOS capacitors with extremely low interface state densities below 10 10 cm %2 eV %1 were obtained by postdeposition annealing, Ga diffusion into overlying SiO 2 layers severely degraded the dielectric breakdown characteristics. However, this problem was found to be solved by rapid thermal processing, leading to the superior performance of the GaN-MOS devices in terms of interface quality, insulating property, and gate dielectric reliability.

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We have demonstrated extremely-thin-body (ETB) (3.5 and 9 nm) InGaAs-on-insulator (InGaAs-OI) MOSFETs on Si substrates with Al 2 O 3 ultrathin buried oxide (UTBOX) layers fabricated by direct wafer bonding (DWB). We have found that the ETB highly-doped InGaAs-OI n-channel MOSFETs without p-n junction can perform a normal MOSFET operation under front-and back-gate configuration and the double-gate operation can provide excellent on-current/offcurrent (I on /I off ) properties of ~10 7 and the improved S factor even for InGaAs-OI MOSFETs with N D of 1×10 19 cm -3 . InstructionIII-V semiconductors are promising candidates as channel materials for future CMOS transistors because of their high electron mobility and low effective mass [1]. We have developed III-V-On-Insulator (III-V-OI) structures with Al 2 O 3 BOX layers using DWB and have demonstrated the In 0.53 Ga 0.47 As-OI MOSFETs (InGaAs body thickness, d InGaAs > 20 nm) on Si with the high electron mobility [2]. In order to apply this device to future technology node CMOS with short gate length L G , the III-V-OI-on-Si structures with ETB less than 10 nm are mandatory. However, the demonstration of III-V-OI MOSFETs with such thin bodies and any analyses of the electrical characteristics have not been reported yet. One of the most critical issues in realizing ETB III-V-OI MOSFETs is the source/drain (S/D) junction formation in ETB III-V-OI films. In order to solve this problem, we newly introduce n-doped accumulation-mode channels without pn junctions [3] to ETB III-V-OI structures fabricated by DWB. This device structure allows us to fabricate MOSFETs without using ion implantation and high temperature activation annealing, which are quite difficult in applying to ETB III-V-OI channels.As a result, we demonstrate, for the first time, the operation of ETB and UTBOX InGaAs-OI n-channel MOSFETs, where the channel thickness is reduced down to 3.5 nm. It is found that the double-gate operation through Al 2 O 3 gate insulators and UTBOXs can yield superior MOSFET performance with high I on /I off ratio of ~10 7 even in the 9-nm-thick InGaAs-OI devices with the doping concentration N D of 1×10 19 cm -3 . We also clarify that the surface roughness plays an import role for the mobility degradation in the ETB III-V-OI MOSFETs with the body thickness less than 10 nm. Simulation and fabrication of n-doped ETB InGaAs-OI MOSFETsThe present ETB InGaAs-OI structure is shown in Fig. 1. Here, the III-V-OI channel regions including S/D are highly doped with n-type impurities and, thus, the MOSFETs have no p-n junctions. Recently, the device operation of Si nanowire MOSFETs with this channel structure has been demonstrated on SOI substrates [3]. In order to examine the applicability of this structure to InGaAs-OI channels, we examine the device characteristics and the device parameter dependence by using device stimulation (Sentaurus).We calculated the device performance of the highly-doped ETB InGaAs-OI MOSFETs. It was assumed here that the work function of a front-gate Ni is 5.1...

Improved nonpolar m-plane (1100) light emitting diode (LED) with a thick InGaN active layer of 8 nm and a thick GaN barrier layer of 37.5 nm for multi-quantum-well (MQW) structure have been fabricated on low extended defect bulk m-plane GaN substrates using metal organic chemical vapor deposition (MOCVD). The peak wavelength of the electroluminescence (EL) emission from the packaged LED was 468 nm. The output power and external quantum efficiency (EQE) were 8.9 mW and 16.8%, respectively, at a DC driving current of 20 mA.

Characteristics of m-plane InGaN/GaN light emitting diodes (LEDs) with various indium compositions were investigated. X-ray diffraction revealed that indium compositions in the InGaN multi quantum wells (MQWs) on m-plane substrate were 2 -3 times lower than those on c-plane substrate. The optical polarization ratio for m-plane LEDs increased from 0.27 to 0.89 with increasing emission wavelength from 383 to 476 nm due to compressively strained InGaN QWs. The output power of electroluminescence decreased above 400 nm although polarization-related internal electric fields were eliminated. #

We have studied the formation of III-V-compound-semiconductors-on-insulator (III-V-OI) structures with thin buried oxide (BOX) layers on Si wafers by using developed direct wafer bonding (DWB). In order to realize III-V-OI MOSFETs with ultrathin body and extremely thin body (ETB) InGaAs-OI channel layers and ultrathin BOX layers, we have developed an electron-cyclotron resonance (ECR) O 2 plasma-assisted DWB process with ECR sputtered SiO 2 BOX layers and a DWB process based on atomic-layer-deposition Al 2 O 3 (ALD-Al 2 O 3 ) BOX layers. It is essential to suppress micro-void generation during wafer bonding process to achieve excellent wafer bonding. We have found that major causes of micro-void generation in DWB processes with ECR-SiO 2 and ALD-Al 2 O 3 BOX layers are desorption of Ar and H 2 O gas, respectively. In order to suppress micro-void generation in the ECR-SiO 2 BOX layers, it is effective to introduce the outgas process before bonding wafers. On the other hand, it is a possible solution for suppressing micro-void generation in the ALD-Al 2 O 3 BOX layers to increase the deposition temperature of the ALD-Al 2 O 3 BOX layers. It is also another possible solution to deposit ALD-Al 2 O 3 BOX layers on thermally oxidized SiO 2 layers, which can absorb the desorption gas from ALD-Al 2 O 3 BOX layers.