A method to bond silicon wafers directly at room temperature was developed. In this method, surfaces of two silicon samples are activated by argon atom beam etching and brought into contact in a vacuum. By the infrared microscope and KOH etching method, no void at the bonded interface was detected in all the specimens tested. In the tensile test, fracture occurred not at the interface but mainly in the bulk of silicon. From these results, it is concluded that the method realizes strong and tight bonding at room temperature and is promising to assemble small parts made by the silicon wafer process.

We increased the light-extraction efficiency (LEE) of AlGaN-based deep-ultraviolet light-emitting diodes (DUV LEDs) by introducing a highly reflective photonic crystal (HR-PhC) into the surface of the p-AlGaN contact layer, thereby achieving a high external quantum efficiency (EQE). A low-damage HR-PhC with a lattice period of approximately 250 nm was fabricated using nanoimprinting and dry etching. A reflective Ni/Mg p-type electrode was deposited on the HR-PhC layer using a tilted-evaporation method. The EQE of a conventional DUV LED with emission around 283 nm was increased from 4.8 to 10% by introducing the HR-PhC and the reflective Ni/Mg electrode. A simple estimation of the effective reflectance of the HR-PhC p-AlGaN contact layer with the Ni/Mg electrode indicated a value exceeding 90%.

Using Ar beam etching in vacuum, strong bonding of Si wafers is attained at room temperature. With appropriate etching time, the bonding occurs spontaneously without any load to force two wafers together. However, surface roughness of the wafers increases during Ar beam etching. Because surface roughness has a strong influence on wafer bonding, long etching time degrades the bonding strength. Using atomic force microscope, we measured surface roughness enhancement caused by Ar beam etching, and investigated the relationship between surface roughness and bonding properties such as strength and interfacial voids. The results agree well with theoretical predictions using elastic theory and energy gain by bond formation. A guideline for successful room-temperature bonding is proposed from these results.

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Silicon wafers are strongly bonded at room temperature by Ar beam surface etching in ultrahigh vacuum. The bonding interface is investigated using a transmission electron microscope (TEM). Residual strain originating from surface roughness exists in the interface region. It is observed only in specimens bonded at room temperature, because it relaxes even by low-temperature annealing at 400°C. An amorphous-like intermediate layer is observed in high-resolution images of the interface. The layer is quite unstable and different from the oxide layer which is often observed at the Si/Si interface prepared by the conventional hydrophilic wafer bonding method. Both annealing and electron beam irradiation during TEM observation cause recrystallization of the layer. The layer contains Ar, but the O concentration is less than the detection limit of analytical TEM. The layer thickness changes according to the kinetic energy of Ar beam. These points demonstrate that Ar atom implantation during the surface etching introduces surface damage, forming the amorphous-like layer.

We have demonstrated thin body III-V-semiconductor-on-insulator (III-V-OI) n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) on a Si wafer fabricated using a novel direct wafer bonding (DWB) process. A 100-nm-thick InGaAs channel was successfully transferred by the low damage and low temperature DWB process using low energy electron cyclotron resonance (ECR) plasma. The transferred InGaAs-OI nMOSFET on the Si wafer exhibited a high electron channel mobility of 1200 cm 2 ÁV À1 Ás À1 , indicating that the present DWB process allows us to form thin III-V-OI channels without serious plasma and bonding damage. This technology is expected to open up the possibility of integrating the ultrathin body III-V-OI MOSFETs on Si platform.

We have demonstrated extremely-thin-body (ETB) (3.5 and 9 nm) InGaAs-on-insulator (InGaAs-OI) MOSFETs on Si substrates with Al 2 O 3 ultrathin buried oxide (UTBOX) layers fabricated by direct wafer bonding (DWB). We have found that the ETB highly-doped InGaAs-OI n-channel MOSFETs without p-n junction can perform a normal MOSFET operation under front-and back-gate configuration and the double-gate operation can provide excellent on-current/offcurrent (I on /I off ) properties of ~10 7 and the improved S factor even for InGaAs-OI MOSFETs with N D of 1×10 19 cm -3 . InstructionIII-V semiconductors are promising candidates as channel materials for future CMOS transistors because of their high electron mobility and low effective mass [1]. We have developed III-V-On-Insulator (III-V-OI) structures with Al 2 O 3 BOX layers using DWB and have demonstrated the In 0.53 Ga 0.47 As-OI MOSFETs (InGaAs body thickness, d InGaAs > 20 nm) on Si with the high electron mobility [2]. In order to apply this device to future technology node CMOS with short gate length L G , the III-V-OI-on-Si structures with ETB less than 10 nm are mandatory. However, the demonstration of III-V-OI MOSFETs with such thin bodies and any analyses of the electrical characteristics have not been reported yet. One of the most critical issues in realizing ETB III-V-OI MOSFETs is the source/drain (S/D) junction formation in ETB III-V-OI films. In order to solve this problem, we newly introduce n-doped accumulation-mode channels without pn junctions [3] to ETB III-V-OI structures fabricated by DWB. This device structure allows us to fabricate MOSFETs without using ion implantation and high temperature activation annealing, which are quite difficult in applying to ETB III-V-OI channels.As a result, we demonstrate, for the first time, the operation of ETB and UTBOX InGaAs-OI n-channel MOSFETs, where the channel thickness is reduced down to 3.5 nm. It is found that the double-gate operation through Al 2 O 3 gate insulators and UTBOXs can yield superior MOSFET performance with high I on /I off ratio of ~10 7 even in the 9-nm-thick InGaAs-OI devices with the doping concentration N D of 1×10 19 cm -3 . We also clarify that the surface roughness plays an import role for the mobility degradation in the ETB III-V-OI MOSFETs with the body thickness less than 10 nm. Simulation and fabrication of n-doped ETB InGaAs-OI MOSFETsThe present ETB InGaAs-OI structure is shown in Fig. 1. Here, the III-V-OI channel regions including S/D are highly doped with n-type impurities and, thus, the MOSFETs have no p-n junctions. Recently, the device operation of Si nanowire MOSFETs with this channel structure has been demonstrated on SOI substrates [3]. In order to examine the applicability of this structure to InGaAs-OI channels, we examine the device characteristics and the device parameter dependence by using device stimulation (Sentaurus).We calculated the device performance of the highly-doped ETB InGaAs-OI MOSFETs. It was assumed here that the work function of a front-gate Ni is 5.1...

A room-temperature wafer bonding method using surface activation by Ar-beam sputter etching were applied to the bonding between dissimilar materials. LiNbO 3 , LiTaO 3 and Gd 3 Ga 5 O 12 wafers were successfully bonded to Si wafers without any heat treatment. This method is free from the various problems caused by the large thermal expansion mismatch between these materials during heat treatment in the conventional wafer bonding processes. The bond prepared by the Ar-beam treatment is so strong that fracture from inside the bulk materials is observed after the tensile test. The results of the bonding of Si wafers to both 128 • Y-cut and Z-cut LiNbO 3 wafers indicate that the influence of the crystal orientation on the bonding strength is negligible in this method. This method provides a very low damage bonding process for various material combinations regardless of any thermal expansion mismatch or crystal lattice mismatch.