A model is presented which relates the applied load and surface roughness to the integrity of metal-metal wafer-level thermocompression bonds. Using contact theory, the true contact area is calculated as a function of the applied load and surface roughness as characterized using atomic force microscopy. The relationship between the nominal and true contact areas quantifies the effects of applied load and surface roughness on the bond integrity of the bonded wafers as indicated by the dicing yield. Experiments on Cu–Cu bonds show that the true contact area provides a better indicator of bond integrity than either the nominal contact area or applied force, taken together or separately.

Ultraviolet photodetector with p-n heterojunction is fabricated by magnetron sputtering deposition of n-type indium gallium zinc oxide (n-IGZO) and p-type nickel oxide (p-NiO) thin films on ITO glass. The performance of the photodetector is largely affected by the conductivity of the p-NiO thin film, which can be controlled by varying the oxygen partial pressure during the deposition of the p-NiO thin film. A highly spectrum-selective ultraviolet photodetector has been achieved with the p-NiO layer with a high conductivity. The results can be explained in terms of the "optically-filtering" function of the NiO layer.

No abstract

The 3 D interconnect technology with Thru Silicon Via (TSV) have gained tremendous advancement in recent years. Final adoption of TSV technologies requires a robust and cost competitive TSV processes. Sidewall plated TSV with polymer filling can reduce half of total process steps from TSV copper (Cu) seed deposition to front-via1 expose. TSV plating time can be reduced ~ 60% for sidewall plated TSV with polymer filling. Costly Cu removal process through chemical mechanical polishing (CMP) can be skipped in sidewall plated TSV with polymer filling process. Wafer warpage and bow for sidewall plated TSV with polymer filling were shown to be ~70% and ~94%, respectively lower than solid Cu filled TSV. Thermal-mechanical simulation show 20% and 42% reduction of shear and bending stress respectively in the case of sidewall plated TSV with polymer filling. IntroductionThe concept of 3D packaging using TSV stacking is one of the most promising technologies. It can extend Moore's Law by stacking and shortening the connection path between memory and logic [2]. Due to the increased in functional integration requirements, more and more assembly house and wafer foundries are looking into 3D TSV technology, which allows stacking of Large Scale Integrated Circuits (LSIs) thereby enabling products to be made smaller with more functionality. 3D technology realizes miniaturization by 300-400% compared to the conventional packaging [3].Although the electrical benefits are greatly increasing in stacked IC packages, their corresponding thermo-mechanical problems are raising as well. This includes problem of coefficient of thermal expansion (CTE) mismatch between copper (~17.5x10 -6 / o C) and silicon (~2.5x10 -6 / o C), heat dissipation, induced stresses, interfacial delimitation, via cracking and so on [1,4,5,6]. Wafer warpage and stress is one of challenge within TSV process integration. Local TSV stress directly decides the TSV performance and reliability. We will focus on wafer warpage and stress comparison for the solid and sidewall plated TSV with polymer filling in this paper. Simulation results were used for the comparison of the local stress in two different approaches.

No abstract

Through-silicon-via (TSV) approach has been widely investigated recently for three-dimensional (3D) electronic packaging integration. TSV wafer warpage is one of the most challenges for successfully subsequent processes. In this work, wafer level warpage modeling methodology has been developed by finite element analysis (FEA) method using equivalent material model. The developed modeling methodology has been verified by numerical results and experiment data. With using the developed model, wafer warpage has been simulated and analyzed by considering different factors such as annealing temperature, Cu overburden thickness, TSV depth and diameter. Simulation results show that wafer warpage increases with increasing annealing temperature and increasing Cu overburden thickness. Such findings have been successfully used in the TSV process optimization to reduce wafer warpage after annealing process. Submodeling methodology has also been developed to determine wafer stress accurately. Wafer bending stress is larger at wafer surface and close to the TSV edge. Bending stress is higher at the edge of TSV with finer pitch.

No abstract

Multilevel high-resistance states are achieved in TiN/HfO x /Pt resistive switching random access memory device by controlling the reset stop voltage. Impedance spectroscopy is used to study the multilevel high-resistance states. It is shown that the high-resistance states can be described with an equivalent circuit consisting of the major components R s , R, and C corresponding to the series resistance of the TiON interfacial layer, the equivalent parallel resistance, and capacitance of the leakage gap between the TiON layer and the residual conductive filament, respectively. These components show a strong dependence on the stop voltage, which can be explained in the framework of oxygen vacancy model and conductive filament concept. On the other hand, R is observed to decrease with dc bias, which can be attributed to the barrier lowering effect of the Coulombic trap well in the Poole-Frenkel emission model. Index Terms-Impedance spectroscopy, multilevel high-resistance states, resistive switching random access memory (RRAM).