Operating TSV in Stable Accumulation Capacitance Region by Utilizing $\hbox{Al}_{2}\hbox{O}_{3}$-Induced Negative Fixed Charge

Zhang, L.; Peng, Lan; Li, H. Y.; Lo, Guo‐Qiang; Kwong, D. L.; Tan, Chuan Seng

doi:10.1109/led.2012.2190968

Cited by 16 publications

(7 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…12. Similar to reported studies, 13) the stability of Al 2 O 3 -induced negative fix charge is also studied under prolonged biasing with a high electric field of 2 MV=cm. The negative fixed charge density is again found to increase initially and plateau after ∼5 h as shown in Fig.…”

Section: Electrical Measurement Resultssupporting

confidence: 55%

“…This improvement further guarantees that the requirements listed in the reported papers 23,24) can be fulfilled. As discussed in previous publications, 13,17,25) V FB is the difference in the work function between Si substrate and the Cu core without the presence of fixed charge (ϕ ms ) and it is estimated to be −0.268 V. In addition, fixed charge (Q f ) can effectively shift the V FB according to V FB = ϕ ms − Q f =C ox . Based on this effect and due to the insertion of ∼10 nm thin Al 2 O 3 layer between Si and the low-k liner, a large amount of negative fixed charge is induced at the liner=Si interface and the charge density is in the order of ∼−1.3 × 10 12 cm −2 .…”

Section: Electrical Measurement Resultsmentioning

confidence: 92%

“…Therefore, operating TSV in the stable but higher value of the accumulation capacitance region within the operating interests of voltage (∼0-5 V) is proposed and demonstrated by utilizing the Al 2 O 3 -induced negative fixed charge between plasma-enhanced tetraethylothosilicate (PETEOS) oxide liner and Si substrate. 13) While the accumulation capacitance (C ox ) is stable, its high capacitance value might not be desirable. To further optimize the TSV capacitance during operation, a combination of lowk and thin Al 2 O 3 layer as the dielectric liner is developed in this work.…”

Section: Introductionmentioning

confidence: 99%

“…Flat-band voltage (V FB ) shift is again achieved by inducing negative fixed charge at the Si=low-k interface with an ultrathin Al 2 O 3 layer so that the TSV operates at stable accumulation capacitance region. 13) Moreover, low-k dielectric with a lower elastic modulus 15) can act as a compliant layer to cushion the thermos-mechanical stress from Cu-TSV to the surrounding Si for better reliability.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Novel integration of ultrathin Al₂O₃ with low-k dielectric as bilayer liner for capacitance optimization and stress mitigation in Cu through-silicon-via

Zhang

Shang

et al. 2016

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

Through-silicon-via (TSV) used in three-dimensional (3D) stacked dies must present small electrical parasitic, such as capacitance, to allow for low latency signal transmission. Stable TSV capacitance is desired to overcome the spatial circuit performance variation caused by non-uniform hot-spot heating. In this work, a novel combination of low-k with ultrathin Al2O3 bilayer liner is successfully integrated in the TSV. The TSV capacitance is reduced by ∼26% as compared to plasma-enhanced tetrahydrothosilicate (PETEOS) oxide liner. Stable TSV capacitance within the operating voltage of interest (∼0–5 V) is achieved by operating the TSV in a stable accumulation capacitance region. The positive shift in the flat-band voltage (ΔV FB = +19 V) is achieved by utilizing Al2O3-induced negative fixed charge (|Q f| = 1.3 × 1012 cm−2) at the Si/low-k interface. Leakage current density of the bilayer liner is improved to a level comparable with the PETEOS oxide liner post annealing [forming gas (N2/H2) at 350 °C for 2 h or 400 °C for 0.5 h]. Low-k material with a smaller elastic modulus improves the thermo-mechanical stress exerted on the surrounding Si substrate compared with PETEOS oxide.

show abstract

Section: Electrical Measurement Resultssupporting

confidence: 55%

Section: Electrical Measurement Resultsmentioning

confidence: 92%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Novel integration of ultrathin Al₂O₃ with low-k dielectric as bilayer liner for capacitance optimization and stress mitigation in Cu through-silicon-via

Zhang

Shang

et al. 2016

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

show abstract

“…Hence, the oxide charge manipulation for TSV engineering, by optimizing all the process parameters, is an efficient way to regulate V FB , offering desired latency under TSV operation [9]- [12]. [20], [21]. The stable TSV accumulation capacitances within the 0 to 5 V range were measured on the Al pads between backside of the wafer and top ring of one TSV.…”

Section: Stable Low Capacitance Design Methods and Implementationmentioning

confidence: 99%

Modeling and Characterization of TSV Capacitor and Stable Low-Capacitance Implementation for Wide-I/O Application

Chang

et al. 2015

IEEE Trans. Device Mater. Relib.

View full text Add to dashboard Cite

Equations of the electric field, surface charge, and silicon capacitance with respect to the surface potential of single through-silicon via (TSV) are derived by Poisson's equation. Four kinds of charges such as the electrons, holes, and ionized donor/acceptor charges in the p-type silicon substrate are brought into the equations. The numerical results of the surface charge show identical plots to planar MOS capacitor when the TSV radius is larger than 1 μm. After presenting the fundamental C-V characteristics of one TSV capacitor, a simple design for gaining a stable low TSV capacitance value within a wide operating window (|V ow | = 20 V) is proposed. Cu TSVs in this design are then demonstrated in the scheme of the wafer-level Cu/Sn to BCB hybrid bonding. The design gives the rational power consumption and delay, and the guideline for physical IC design is described in this paper. Without the oxide-trapped charge Q ot engineering in TSV oxide liner, neither considerations of the V FB shifts nor the doping-type selection in silicon substrate, the design facilitates IC engineers to plan the high-speed TSVs at a specific location and to save the cost from TSV engineering simultaneously. Index Terms-C-Vcharacteristics, modeling, threedimensional integrated circuit (3DIC), through-silicon via (TSV).

show abstract

Low capacitance and highly reliable blind through-silicon-vias (TSVs) with vacuum-assisted spin coating of polyimide dielectric liners

Yan

Xiong

Liu

et al. 2016

Sci. China Technol. Sci.

View full text Add to dashboard Cite

Operating TSV in Stable Accumulation Capacitance Region by Utilizing $\hbox{Al}_{2}\hbox{O}_{3}$-Induced Negative Fixed Charge

Cited by 16 publications

References 12 publications

Novel integration of ultrathin Al₂O₃ with low-k dielectric as bilayer liner for capacitance optimization and stress mitigation in Cu through-silicon-via

Novel integration of ultrathin Al₂O₃ with low-k dielectric as bilayer liner for capacitance optimization and stress mitigation in Cu through-silicon-via

Modeling and Characterization of TSV Capacitor and Stable Low-Capacitance Implementation for Wide-I/O Application

Low capacitance and highly reliable blind through-silicon-vias (TSVs) with vacuum-assisted spin coating of polyimide dielectric liners

Contact Info

Product

Resources

About

Operating TSV in Stable Accumulation Capacitance Region by Utilizing $\hbox{Al}_{2}\hbox{O}_{3}$-Induced Negative Fixed Charge

Cited by 16 publications

References 12 publications

Novel integration of ultrathin Al2O3 with low-k dielectric as bilayer liner for capacitance optimization and stress mitigation in Cu through-silicon-via

Novel integration of ultrathin Al2O3 with low-k dielectric as bilayer liner for capacitance optimization and stress mitigation in Cu through-silicon-via

Modeling and Characterization of TSV Capacitor and Stable Low-Capacitance Implementation for Wide-I/O Application

Low capacitance and highly reliable blind through-silicon-vias (TSVs) with vacuum-assisted spin coating of polyimide dielectric liners

Contact Info

Product

Resources

About

Novel integration of ultrathin Al₂O₃ with low-k dielectric as bilayer liner for capacitance optimization and stress mitigation in Cu through-silicon-via

Novel integration of ultrathin Al₂O₃ with low-k dielectric as bilayer liner for capacitance optimization and stress mitigation in Cu through-silicon-via