3D interconnection process development and integration with low stress TSV

Abstract

The 3 D interconnect technology with Thru Silicon Via (TSV) have gained tremendous advancement in recent years. Final adoption of TSV technologies requires a robust and cost competitive TSV processes. Sidewall plated TSV with polymer filling can reduce half of total process steps from TSV copper (Cu) seed deposition to front-via1 expose. TSV plating time can be reduced ~ 60% for sidewall plated TSV with polymer filling. Costly Cu removal process through chemical mechanical polishing (CMP) can be skipped in sidewall plated TSV with polymer filling process. Wafer warpage and bow for sidewall plated TSV with polymer filling were shown to be ~70% and ~94%, respectively lower than solid Cu filled TSV. Thermal-mechanical simulation show 20% and 42% reduction of shear and bending stress respectively in the case of sidewall plated TSV with polymer filling. IntroductionThe concept of 3D packaging using TSV stacking is one of the most promising technologies. It can extend Moore's Law by stacking and shortening the connection path between memory and logic [2]. Due to the increased in functional integration requirements, more and more assembly house and wafer foundries are looking into 3D TSV technology, which allows stacking of Large Scale Integrated Circuits (LSIs) thereby enabling products to be made smaller with more functionality. 3D technology realizes miniaturization by 300-400% compared to the conventional packaging [3].Although the electrical benefits are greatly increasing in stacked IC packages, their corresponding thermo-mechanical problems are raising as well. This includes problem of coefficient of thermal expansion (CTE) mismatch between copper (~17.5x10 -6 / o C) and silicon (~2.5x10 -6 / o C), heat dissipation, induced stresses, interfacial delimitation, via cracking and so on [1,4,5,6]. Wafer warpage and stress is one of challenge within TSV process integration. Local TSV stress directly decides the TSV performance and reliability. We will focus on wafer warpage and stress comparison for the solid and sidewall plated TSV with polymer filling in this paper. Simulation results were used for the comparison of the local stress in two different approaches.

Electrical transmission characteristics of differential TSV structures in 3D TSV packaging

“…[1][2][3] Many studies have been carried out in the field of electrical characteristics of TSV, but most studies focused on the single-ended transmission characteristic of TSV. [4][5][6] In-depth study of the transmission characteristics in differential TSV structure is almost vacant.…”

3D integration review

“…Any missing seed, for instance, could lead to plating issues. Detailed studies of copper plating problems, and ways to overcome them can be found in several recent publications [29,[33][34][35]37]. Further, annealing studies on the copper TSV have been conducted, and results reported in [42].…”

“…Aspect ratios of better than 40:1 are achievable by this method. Several researchers have used the Bosch method for their TSV evaluations [25,27,28,34,42]. Others have investigated non-Bosch TSV etch processes, such as a magnetically-enhanced capacitively-coupled plasma etch method, to achieve aspect ratios approaching 30:1 [30] or an enhanced etch process to achieve deep vias with minimal sidewall roughness, i.e.…”

“…polymers, followed by appropriate thermal processing and removal of excess material from the surface. Extensive work has been done in the development of each of these processes, and the characterization of the resulting TSV's at a variety of dimensions and pitches [24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43].…”

Thermal and Electrical Reliability Tests of Air-Gap Through-Silicon Vias

“…To alleviate the thermal stresses, configurations with a stress buffer layer have been proposed, and embodiments of TSVs with stress buffer layers have been developed using polymer insulators [28]- [30], open configuration [31], or polymer cores in annular conductors [32], [33]. Polymers are effective in reducing thermal stresses due to the low elastic modulus and the ease of deformation [34]- [37].…”