The swing at the output of the driver is determined by This paper describes a low-power self-terminated the attenuation of the channel and the sensitivity of the transmitter. A novel architecture is proposed to perform receiver. In this design the target sensitivity of the receiver is impedance matching and channel equalization with low <35mV. The pre-distortion design handles 14dB loss of 6.5 power consumption. The test chip is fabricated using 0.18-pm meters of RG55 or 80 centimeters of FR-4 20 mils PCB at digital CMOS process with 1.8-V supply. The transmitter 1.8GHz. operates at 3.6Gbps and consumes 9.66mW. The total NMOS devices are used for both pull-up and pull-down transmitter area is 0.072 mm2.to minimize device size and capacitance. The source Abstract This paper describes a 3.6-Gbps 27-mW transceiver for chip-to-chip applications. A novel data receiving and timing recovery technique are presented with very low power penalties while maintaining high signal integrity. The input comparator filters noise with built-in bandwidth control and digital offset compensation while consuming 300uW. Static phase offset introduced onto the charge-pump permits phase recovery with no additional power. The entire design occupies 0.2mmz in a 0.18-um 1.8-V CMOS technology.
This paper presents a power-and area-efficient multistandard serial link transceiver designed for backplane application rates of up to 28 Gb/s, such as OIF CEI-25G, CEI-28G, and IEEE 802.3bj 100G-KR4. The receiver features a continuous-time linear equalizer, variable gain amplifier, and a 14-tap decision feedback equalizer, including eight floating taps. The transmitter has a 2:1 multiplexer with a duty cycle distortion corrected half-rate clock and a full-rate source-series terminated driver with a 5-tap feed-forward equalizer. The shared PLL employs a transformer-based LC-VCO that achieves a VCO tuning range of 20G to 29 GHz and 0.23 ps RMS jitter at 28.125 GHz. The transmitter output shows only 50 fs duty-cycle distortion. The transceiver can compensate a 40 dB insertion loss backplane channel (excluding package) at a data rate of 25.78 Gb/s with eight channels running simultaneously. It is fabricated in 28 nm standard CMOS and analog section consumes only 295 mW at 1 V supply with transmitter driver at 1.25 V. Such low power consumption and performance are achieved by combination of advanced 28 nm process, low power and performance driven receiver and transmitter topologies, widely adopted bandwidth extension techniques, built-in analog calibrations and one common PLL with a transformer based VCO for four transceivers.Index Terms-Backplane, continuous-time linear equalizer, decision feedback equalizer, duty-cycle distortion, feed-forward equalizer, 40 dB insertion loss, quarter-rate topology, serial link transceiver, source-series terminated driver, tap timing, 25G.
Power dissipation of multi-gigabit per second parallel input-output (I/O) links is an integral part of total integrated circuits (IC) power dissipation. This brief presents an optimal data rate per I/O link at which the power dissipation is minimized. The data rate is expressed as a function of the transmission channel's frequency response. The impact of considering the power due to on-chip electronic switching depends on the process technology of the IC. The analysis results show that an upper bound for the data rate exists based on the channel's frequency response and that the upper bound is being approached with more advanced process technologies.
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